Using mbtb basetable align

src/cpu/pred/BranchPredictor.py

@@ -985,6 +985,7 @@ class MBTB(TimedBaseBTBPredictor):
     blockSize = 32  # max 64 byte block, 32 byte aligned
     # MBTB is always half-aligned - no parameter needed
     victimCacheSize = Param.Unsigned(0, "Number of entries in the victim cache")
+    usingMbtbBaseEiterTage = Param.Bool(True, "Whether using MBTB basetable either TAGE ")
 
 class AheadBTB(TimedBaseBTBPredictor):
     type = 'AheadBTB'
@@ -1060,6 +1061,7 @@ class BTBTAGE(TimedBaseBTBPredictor):
     numBanks = Param.Unsigned(4, "Number of banks for bank conflict simulation")
     enableBankConflict = Param.Bool(True, "Enable bank conflict simulation")
     numDelay = 2
+    usingMbtbBaseEiterTage = Param.Bool(True, "Whether using MBTB basetable either TAGE ")
 
 class MicroTAGE(BTBTAGE):
     """A smaller TAGE predictor configuration to assist uBTB"""

src/cpu/pred/btb/btb_tage.cc

@@ -91,6 +91,7 @@ indexShift(bankBaseShift + ceilLog2(p.numBanks)),
 enableBankConflict(p.enableBankConflict),
 lastPredBankId(0),
 predBankValid(false),
+usingBasetable( !p.usingMbtbBaseEiterTage),
 tageStats(this, p.numPredictors, p.numBanks)
 {
     this->needMoreHistories = p.needMoreHistories;
@@ -269,7 +270,9 @@ BTBTAGE::generateSinglePrediction(const BTBEntry &btb_entry,
     // Use base table instead of btb_entry.ctr
     Addr base_idx = getBaseTableIndex(startPC);
     unsigned branch_idx = getBranchIndexInBlock(btb_entry.pc, startPC);
-    bool base_taken = getDelay() != 0 ? baseTable[base_idx][branch_idx] >= 0 : btb_entry.ctr >= 0;
+    bool base_taken = getDelay() != 0 ? (usingBasetable ? baseTable[base_idx][branch_idx] >= 0 : btb_entry.ctr >= 0)
+                                                                                     : btb_entry.ctr >= 0;
+    //bool base_taken = btb_entry.ctr >= 0;
     bool alt_pred = alt_provided ? alt_taken : base_taken; // if alt provided, use alt prediction, otherwise use base
 
     // use_alt_on_na gating: when provider weak, consult per-PC counter

src/cpu/pred/btb/btb_tage.hh

@@ -315,6 +315,7 @@ class BTBTAGE : public TimedBaseBTBPredictor
     // Track last prediction bank for conflict detection
     unsigned lastPredBankId;         // Bank ID of last prediction
     bool predBankValid;              // Whether lastPredBankId is valid
+    bool usingBasetable;          // Whether using basetable for either MBTB or TAGE
 
 #ifdef UNIT_TEST
     typedef uint64_t Scalar;

src/cpu/pred/btb/mbtb.cc

@@ -81,6 +81,7 @@ MBTB::MBTB(const Params &p)
     numEntries(p.numEntries),
     numWays(p.numWays),
     tagBits(p.tagBits),
+    usingBasetable(p.usingMbtbBaseEiterTage),
     btbStats(this, p.numWays)
 {
     // MBTB doesn't support ahead-pipelined stages
@@ -356,7 +357,7 @@ MBTB::lookupSingleBlock(Addr block_pc)
     for (auto &way : btb_set) {
         if (way.valid && way.tag == current_tag) {
             res.push_back(way);
-            way.tick = curTick();  // Update timestamp for MRU
+            way.tick = curTick(); // Update timestamp for MRU
             std::make_heap(target_mru[btb_idx].begin(), target_mru[btb_idx].end(), older());
         }
     }
@@ -689,12 +690,44 @@ MBTB::update(const FetchStream &stream)
     // 1. Check prediction hit status, for stats recording
     checkPredictionHit(stream,
         std::static_pointer_cast<BTBMeta>(stream.predMetas[getComponentIdx()]).get());
+    if (!usingBasetable) {
+        // only update btb entry for control squash T-> NT or NT -> T
+        if (stream.squashType == SQUASH_CTRL) {
+            warn_if(stream.exeBranchInfo.pc > stream.updateEndInstPC, "exeBranchInfo.pc > updateEndInstPC");
+            updateBTBEntry(stream.exeBranchInfo, stream);
+        }
+    }else {
+        auto entries_need_update = prepareUpdateEntries(stream);
+        for (auto &entry : entries_need_update) {
+            updateBTBEntry(entry, stream);
+        }
+    }
+
+}
+
 
-    // only update btb entry for control squash T-> NT or NT -> T
-    if (stream.squashType == SQUASH_CTRL) {
-        warn_if(stream.exeBranchInfo.pc > stream.updateEndInstPC, "exeBranchInfo.pc > updateEndInstPC");
-        updateBTBEntry(stream.exeBranchInfo, stream);
+std::vector<BTBEntry>
+MBTB::prepareUpdateEntries(const FetchStream &stream) {
+    auto all_entries = stream.updateBTBEntries;
+
+    // Add potential new BTB entry if it's a btb miss during prediction
+    if (!stream.updateIsOldEntry) {
+        BTBEntry potential_new_entry = stream.updateNewBTBEntry;
+        bool new_entry_taken = stream.exeTaken && stream.getControlPC() == potential_new_entry.pc;
+        if (!new_entry_taken) {
+            potential_new_entry.alwaysTaken = false;
+        }
+        all_entries.push_back(potential_new_entry);
     }
+
+    // Filter: only keep conditional branches that are not always taken
+    if (getResolvedUpdate()) {
+        auto remove_it = std::remove_if(all_entries.begin(), all_entries.end(),
+            [](const BTBEntry &e) { return !e.resolved; });
+        all_entries.erase(remove_it, all_entries.end());
+    }
+
+    return all_entries;
 }
 
 /**

src/cpu/pred/btb/mbtb.hh

@@ -170,6 +170,8 @@ class MBTB : public TimedBaseBTBPredictor
      */
     void update(const FetchStream &stream) override;
 
+    std::vector<BTBEntry> prepareUpdateEntries(const FetchStream &stream);
+
     void printBTBEntry(const BTBEntry &e, uint64_t tick = 0) {
         DPRINTF(BTB, "BTB entry: valid %d, pc:%#lx, tag: %#lx, size:%d, target:%#lx, \
             cond:%d, indirect:%d, call:%d, return:%d, always_taken:%d, tick:%lu\n",
@@ -393,6 +395,7 @@ class MBTB : public TimedBaseBTBPredictor
     /** Address calculation masks and shifts */
     Addr idxMask;          // Mask for extracting index bits
     unsigned tagBits;      // Number of tag bits
+    bool usingBasetable;   // Whether using basetable for either MBTB or TAGE
     Addr tagMask;          // Mask for extracting tag bits
     unsigned idxShiftAmt;  // Amount to shift PC for index
     unsigned tagShiftAmt;  // Amount to shift PC for tag

src/cpu/pred/btb/stream_struct.hh

@@ -86,6 +86,7 @@ struct BranchInfo
     bool resolved;
     bool isCond;
     bool isIndirect;
+    bool isDirect;
     bool isCall;
     bool isReturn;
     uint8_t size;
@@ -103,6 +104,7 @@ struct BranchInfo
           resolved(false),
           isCond(static_inst->isCondCtrl()),
           isIndirect(static_inst->isIndirectCtrl()),
+          isDirect(static_inst->isDirectCtrl()),
           isCall(static_inst->isCall()),
           isReturn(static_inst->isReturn() && !static_inst->isNonSpeculative() && !static_inst->isDirectCtrl()),
           size(size)

src/cpu/pred/btb/test/btb.test.cc

@@ -132,6 +132,10 @@ predictUpdateCycle(MBTB* btb,
         btb->getAndSetNewBTBEntry(stream);
     }
 
+    for (auto &entry : stream.updateBTBEntries) {
+        entry.resolved = true;
+    }
+
     btb->update(stream);
 
     // Return final predictions after update