cpu-o3: rename execWB to toCommit wire for instruction squashing#678
cpu-o3: rename execWB to toCommit wire for instruction squashing#678jensen-yan merged 2 commits intoxs-devfrom
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- delete old toCommit and execBypass - Updated the IEW class to replace execWB with toCommit for handling instruction squashing and commit signals. - Enhanced comments to clarify the purpose of the toCommit wire and its zero-cycle latency communication with Commit. Change-Id: I43ab0206c70ea3d7152a40bd8f589dc8de164cc9
📝 WalkthroughWalkthroughConsolidates IEW→Commit signaling by replacing Changes
Sequence Diagram(s)sequenceDiagram
%%{init: {"themeVariables": {"primaryColor":"#9ad3bc","secondaryColor":"#f7f3d7","actorBorder":"#6a9fb5"}}}%%
participant Exec as Execute
participant IEW as IEW
participant Commit as Commit
note over IEW,Commit: toCommit wire (iewToCommitDelay)
Exec->>IEW: completed instruction (+ signals)
IEW->>IEW: populate toCommit fields
IEW-->>Commit: toCommit (delayed by iewToCommitDelay)
alt squash/mispredict
Commit->>IEW: squash request
IEW->>Exec: propagate squash
end
Commit->>Commit: commit / retire instruction
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~25 minutes Suggested labels
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✅ Passed checks (2 passed)
✨ Finishing touches
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- Replaced wbDelay with iewToCommitDelay in the IEW class to clarify the delay between IEW and Commit. - Updated comments to reflect the new variable and its role in achieving zero-cycle latency for IEW to Commit communication. Change-Id: I43ab0206c70ea3d7152a40bd8f589dc8de164cc9
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Actionable comments posted: 1
📜 Review details
Configuration used: defaults
Review profile: CHILL
Plan: Pro
📒 Files selected for processing (3)
src/cpu/o3/BaseO3CPU.pysrc/cpu/o3/iew.ccsrc/cpu/o3/iew.hh
💤 Files with no reviewable changes (1)
- src/cpu/o3/BaseO3CPU.py
🚧 Files skipped from review as they are similar to previous changes (1)
- src/cpu/o3/iew.hh
🔇 Additional comments (6)
src/cpu/o3/iew.cc (6)
92-92: LGTM! Clear naming improvement.The rename from
wbDelaytoiewToCommitDelayimproves code clarity by explicitly indicating this delay governs the IEW→Commit path.
565-588: LGTM! Consistent refactoring.All references to
execWBhave been correctly updated totoCommitthroughout the branch misprediction handling. The logic remains unchanged, and the new naming better reflects the purpose of signaling commit about squash events.
604-626: LGTM! Consistent memory violation handling.The rename from
execWBtotoCommitis properly applied throughout the memory order violation squash logic. All field accesses are correctly updated while preserving the original logic.
1577-1579: LGTM! Correct conditional check.The condition properly references
toCommit->squash[tid]andtoCommit->squashedSeqNum[tid]to determine whether to process misprediction after execution, consistent with the wire renaming.
1820-1821: LGTM! Writeback path correctly updated.The instruction writeback loop properly accesses
toCommit->insts[inst_num]instead of the oldexecWBreference, maintaining consistency with the wire renaming throughout the IEW stage.
2046-2047: LGTM! Misprediction check correctly updated.The conditional in
checkMisprediction()properly referencestoCommit->squash[tid]andtoCommit->squashedSeqNum[tid], consistent with the wire renaming across all squash handling paths.
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[Generated by GEM5 Performance Robot] Align BTB PerformanceOverall Score
[Generated by GEM5 Performance Robot] Align BTB PerformanceOverall Score
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Change-Id: I43ab0206c70ea3d7152a40bd8f589dc8de164cc9
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