cpu-o3: change idealkmhv3 config

[edwu186]

loadFusion: True -> Fasle
store prefetch train: True -> False
simulate dcache refill: Flase -> True
L2 replacement policy: enable XSDRRIPRP

Change-Id: I0b7b2a68219cc8b570c5df8df8f87004f279b652

Summary by CodeRabbit

• Chores
  • Updated CPU simulation configuration to improve overall cache performance modeling
  • Enabled L1 data cache refill simulation for more accurate cache behavior tracking
  • Reconfigured L2 cache replacement policies with new per-slice configuration options
  • Fine-tuned prefetch training and load fusion parameters to optimize simulation behavior

_{✏️ Tip: You can customize this high-level summary in your review settings.}

[coderabbitai]

📝 Walkthrough

Walkthrough

Configuration adjustments to CPU and cache simulation parameters in an example configuration file, including disabling CPU load fusion, adding a store prefetch flag, enabling L1 cache simulation, and updating L2 cache replacement policy settings.

Changes

Cohort / File(s)	Summary
Configuration Updates configs/example/idealkmhv3.py	Disabled CPU load fusion, introduced store_prefetch_train flag, enabled L1 data cache simulation refill, and configured L2 cache replacement policy with XSDRRIPRP(mode=2, num_sets=1024) for each slice

Estimated code review effort

🎯 1 (Trivial) | ⏱️ ~3 minutes

Suggested labels

perf

Suggested reviewers

• happy-lx
• tastynoob

Poem

Caches dance with XSDRRIPRP flair,
Load fusion rests, prefetch takes care,
Simulation blooms on L1's floor,
Configs tune the silicon's core! 🐰✨

Pre-merge checks and finishing touches

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%.	You can run @coderabbitai generate docstrings to improve docstring coverage.

✅ Passed checks (2 passed)

Check name	Status	Explanation
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.
Title check	✅ Passed	The PR title 'cpu-o3: change idealkmhv3 config' accurately describes the main change: modifying configuration parameters in the idealkmhv3.py file for the CPU O3 model.

✨ Finishing touches

• 📝 Generate docstrings

---

📜 Recent review details

Configuration used: defaults

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 4ec9fc8 and 6e5b39c.

📒 Files selected for processing (1)

• configs/example/idealkmhv3.py

🧰 Additional context used

🧬 Code graph analysis (1)

configs/example/idealkmhv3.py (1)

src/mem/cache/replacement_policies/ReplacementPolicies.py (1)

• XSDRRIPRP (158-166)

🪛 Ruff (0.14.10)

configs/example/idealkmhv3.py

105-105: XSDRRIPRP may be undefined, or defined from star imports

(F405)

⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (2)

• GitHub Check: Quick Build, Unit Tests & Smoke Test
• GitHub Check: perf_test / XS-GEM5 - Run performance test (spec06-0.8c)

🔇 Additional comments (4)

configs/example/idealkmhv3.py (4)

34-34: LGTM: Load fusion disabled as intended.

The change aligns with the PR objectives to disable load fusion optimization.

---

89-89: LGTM: DCache refill simulation enabled as intended.

The change aligns with the PR objectives to enable simulation of data cache refills.

---

76-76: No issues found. The store_prefetch_train parameter is properly defined in the CPU model (src/cpu/o3/BaseO3CPU.py) as Param.Bool(True, ...) and is correctly recognized and used throughout the codebase. The assignment on line 76 is valid.

---

102-105: No issues found. XSDRRIPRP is properly accessible via the star import from m5.objects (which uses dynamic module loading). The configuration is correct: mode=2 specifies DRRIP (Set Dueling) and num_sets=1024 correctly matches the L2 slice geometry (512KB / 8-way / 64B line). The static analysis flag is a false positive due to the intentional use of star imports in this codebase's module loading pattern.

---

Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out.

❤️ Share

• X
• Mastodon
• Reddit
• LinkedIn

_{Comment @coderabbitai help to get the list of available commands and usage tips.}

[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.1772	-
This PR	2.1772	➡️ 0.0000 (0.00%)

✅ Difftest smoke test passed!

[XiangShanRobot]

[Generated by GEM5 Performance Robot]
commit: 6e5b39c
workflow: gem5 Ideal BTB Performance Test

Ideal BTB Performance

Overall Score

	PR	Master	Diff(%)
Score	19.90	20.07	-0.81 🔴