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Merged
tastynoob merged 1 commit into from
Jan 29, 2026
Merged

cpu-pred-btb: remove fetch stream use fetch target #744

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8 changes: 3 additions & 5 deletions src/cpu/o3/comm.hh
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Original file line number Diff line number Diff line change
Expand Up @@ -147,7 +147,6 @@ struct IEWStruct
DynInstPtr mispredictInst[MaxThreads];
Addr mispredPC[MaxThreads];
InstSeqNum squashedSeqNum[MaxThreads];
uint64_t squashedStreamId[MaxThreads];
uint64_t squashedTargetId[MaxThreads];
uint64_t squashedLoopIter[MaxThreads];
std::unique_ptr<PCStateBase> pc[MaxThreads];
Expand Down Expand Up @@ -196,7 +195,7 @@ struct SquashVersion

struct ResolveQueueEntry
{
uint64_t resolvedFSQId;
uint64_t resolvedFTQId;
std::vector<uint64_t> resolvedInstPC;
};

Expand Down Expand Up @@ -250,7 +249,7 @@ struct TimeStruct

struct ResolvedCFIEntry
{
uint64_t fsqId;
uint64_t ftqId;
uint64_t pc;
};
/** Resolved control-flow PCs produced this cycle (fetch buffers/merges). */
Expand Down Expand Up @@ -301,8 +300,7 @@ struct TimeStruct

InstSeqNum doneMemSeqNum;

uint64_t doneFsqId; // F
uint64_t squashedStreamId; // F
uint64_t doneFtqId; // F
uint64_t squashedTargetId; // F
unsigned squashedLoopIter; // F

Expand Down
10 changes: 2 additions & 8 deletions src/cpu/o3/commit.cc
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Expand Up @@ -701,7 +701,6 @@ Commit::squashAll(ThreadID tid)

set(toIEW->commitInfo[tid].pc, pc[tid]);

toIEW->commitInfo[tid].squashedStreamId = committedStreamId;
toIEW->commitInfo[tid].squashedTargetId = committedTargetId;
toIEW->commitInfo[tid].squashedLoopIter = committedLoopIter;

Expand Down Expand Up @@ -1074,12 +1073,9 @@ Commit::commit()
DPRINTF(Commit,
"Unable to find squashed instruction in ROB\n");
}
toIEW->commitInfo[tid].squashedStreamId = fromIEW->squashedStreamId[tid];
toIEW->commitInfo[tid].squashedTargetId = fromIEW->squashedTargetId[tid];
toIEW->commitInfo[tid].squashedLoopIter = fromIEW->squashedLoopIter[tid];

// toIEW->commitInfo[tid].doneFsqId =
// toIEW->commitInfo[tid].squashInst->getFsqId();
if (toIEW->commitInfo[tid].mispredictInst) {
if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
toIEW->commitInfo[tid].branchTaken = true;
Expand Down Expand Up @@ -1322,11 +1318,9 @@ Commit::commitInsts()
// Set the doneSeqNum to the youngest committed instruction.
toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;

if (head_inst->getFsqId() > 1) {
toIEW->commitInfo[tid].doneFsqId =
head_inst->getFsqId() - 1;
if (head_inst->getFtqId() > 1) {
toIEW->commitInfo[tid].doneFtqId = head_inst->getFtqId() - 1;
}
committedStreamId = head_inst->getFsqId();
committedTargetId = head_inst->getFtqId();
committedLoopIter = head_inst->getLoopIteration();

Expand Down
3 changes: 1 addition & 2 deletions src/cpu/o3/commit.hh
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Expand Up @@ -554,8 +554,7 @@ private:

// committed Stream and Target

uint64_t committedStreamId{1};
uint64_t committedTargetId{0};
uint64_t committedTargetId{1};
uint64_t committedLoopIter{};

struct CommitStats : public statistics::Group
Expand Down
1 change: 0 additions & 1 deletion src/cpu/o3/decode.cc
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Expand Up @@ -1012,7 +1012,6 @@ Decode::checkAndFuseInsts(std::vector<DynInstPtr> &vec, DynInstPtr& cur)
instruction->setVersion(inst_pair[1]->getVersion());
instruction->setTid(inst_pair[1]->threadNumber);
instruction->thread = inst_pair[1]->thread;
instruction->setFsqId(inst_pair[1]->fsqId);
instruction->setFtqId(inst_pair[1]->ftqId);

instruction->instListIt = cpu->instList.insert(inst_pair[0]->instListIt, instruction);
Expand Down
16 changes: 1 addition & 15 deletions src/cpu/o3/dyn_inst.hh
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Expand Up @@ -395,10 +395,8 @@ class DynInst : public ExecContext, public RefCounted

Addr fallThruPC;

/** fsqId and ftqId are used for squashing and committing */
/** ftqId is used for squashing and committing */
/** The fetch stream queue ID of the instruction. */
unsigned fsqId;
/** The fetch target queue ID of the instruction. */
unsigned ftqId;
/** The number of loop iteration within an fsq entry of the instruction. */
unsigned loopIteration;
Expand Down Expand Up @@ -1558,18 +1556,6 @@ class DynInst : public ExecContext, public RefCounted
}


void
setFsqId(unsigned id)
{
fsqId = id;
}

unsigned
getFsqId()
{
return fsqId;
}

void
setFtqId(unsigned id)
{
Expand Down
52 changes: 23 additions & 29 deletions src/cpu/o3/fetch.cc
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Expand Up @@ -629,8 +629,8 @@ Fetch::processCacheCompletion(PacketPtr pkt)
}

// Verify fetchBufferPC alignment with the supplying FSQ entry.
if (fetchBuffer[tid].valid && dbpbtb->fsqHasHead()) {
const auto &stream = dbpbtb->fsqHead();
if (fetchBuffer[tid].valid && dbpbtb->ftqHasHead()) {
const auto &stream = dbpbtb->ftqHead();
if (fetchBuffer[tid].startPC != stream.startPC) {
panic("fetchBufferPC %#x should be aligned with FSQ startPC %#x",
fetchBuffer[tid].startPC, stream.startPC);
Expand Down Expand Up @@ -782,10 +782,8 @@ Fetch::lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &next_pc)
// Decoupled+BTB-only: compute next PC directly from the supplying FSQ entry.
ThreadID tid = inst->threadNumber;
assert(dbpbtb);
assert(dbpbtb->fsqHasHead());
const auto &stream = dbpbtb->fsqHead();
const auto fsq_id = dbpbtb->fsqHeadId();
const auto ftq_id = dbpbtb->fsqHeadFtqId();
assert(dbpbtb->ftqHasHead());
const auto &stream = dbpbtb->ftqHead();

const Addr curr_pc = next_pc.instAddr();
assert(stream.startPC <= curr_pc && curr_pc < stream.predEndPC);
Expand Down Expand Up @@ -818,7 +816,7 @@ Fetch::lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &next_pc)
// Track how many dynamic instructions were fetched for this (legacy) FTQ/FSQ entry.
ftqEntryFetchedInsts[tid]++;
if (run_out) {
dbpbtb->consumeFetchTarget(ftq_id, fsq_id, ftqEntryFetchedInsts[tid]);
dbpbtb->consumeFetchTarget(ftqEntryFetchedInsts[tid]);
ftqEntryFetchedInsts[tid] = 0;
fetchBuffer[tid].valid = false;
DPRINTF(DecoupleBP, "Used up fetch targets.\n");
Expand Down Expand Up @@ -1519,7 +1517,7 @@ Fetch::handleIEWSignals()
for (const auto &resolved : incoming) {
bool merged = false;
for (auto &queued : resolveQueue) {
if (queued.resolvedFSQId == resolved.fsqId) {
if (queued.resolvedFTQId == resolved.ftqId) {
queued.resolvedInstPC.push_back(resolved.pc);
merged = true;
break;
Expand All @@ -1531,7 +1529,7 @@ Fetch::handleIEWSignals()
}

ResolveQueueEntry new_entry;
new_entry.resolvedFSQId = resolved.fsqId;
new_entry.resolvedFTQId = resolved.ftqId;
new_entry.resolvedInstPC.push_back(resolved.pc);
resolveQueue.push_back(std::move(new_entry));
enqueueCount++;
Expand All @@ -1543,7 +1541,7 @@ Fetch::handleIEWSignals()

if (!resolveQueue.empty()) {
auto &entry = resolveQueue.front();
unsigned int stream_id = entry.resolvedFSQId;
unsigned int stream_id = entry.resolvedFTQId;
dbpbtb->prepareResolveUpdateEntries(stream_id);
for (const auto resolvedInstPC : entry.resolvedInstPC) {
dbpbtb->markCFIResolved(stream_id, resolvedInstPC);
Expand All @@ -1564,10 +1562,10 @@ Fetch::handleCommitSignals(ThreadID tid)
{
// Check squash signals from commit.
if (!fromCommit->commitInfo[tid].squash) {
if (fromCommit->commitInfo[tid].doneSeqNum) {
DPRINTF(DecoupleBP, "Commit stream Id: %lu\n", fromCommit->commitInfo[tid].doneFsqId);
if (fromCommit->commitInfo[tid].doneFtqId) {
DPRINTF(DecoupleBP, "Commit stream Id: %lu\n", fromCommit->commitInfo[tid].doneFtqId);
assert(dbpbtb);
dbpbtb->update(fromCommit->commitInfo[tid].doneFsqId, tid);
dbpbtb->update(fromCommit->commitInfo[tid].doneFtqId, tid);
}
return false;
}
Expand Down Expand Up @@ -1602,24 +1600,22 @@ Fetch::handleCommitSignals(ThreadID tid)
DPRINTF(Fetch, "Use mispred inst to redirect, treating as control squash\n");
const auto corr_pc = fromCommit->commitInfo[tid].pc->as<RiscvISA::PCState>();
assert(dbpbtb);
dbpbtb->controlSquash(mispred_inst->getFtqId(), mispred_inst->getFsqId(), mispred_inst->pcState(),
dbpbtb->controlSquash(mispred_inst->getFtqId(), mispred_inst->pcState(),
corr_pc, mispred_inst->staticInst,
mispred_inst->getInstBytes(), fromCommit->commitInfo[tid].branchTaken,
mispred_inst->seqNum, tid, mispred_inst->getLoopIteration(), true);
} else if (fromCommit->commitInfo[tid].isTrapSquash) {
DPRINTF(Fetch, "Treating as trap squash\n", tid);
const auto trap_pc = fromCommit->commitInfo[tid].pc->as<RiscvISA::PCState>();
assert(dbpbtb);
dbpbtb->trapSquash(fromCommit->commitInfo[tid].squashedTargetId,
fromCommit->commitInfo[tid].squashedStreamId, fromCommit->commitInfo[tid].committedPC,
dbpbtb->trapSquash(fromCommit->commitInfo[tid].squashedTargetId, fromCommit->commitInfo[tid].committedPC,
trap_pc, tid, fromCommit->commitInfo[tid].squashedLoopIter);
} else {
if (fromCommit->commitInfo[tid].pc && fromCommit->commitInfo[tid].squashedStreamId != 0) {
if (fromCommit->commitInfo[tid].pc && fromCommit->commitInfo[tid].squashedTargetId != 0) {
DPRINTF(Fetch, "Squash with stream id and target id from IEW\n");
const auto nc_pc = fromCommit->commitInfo[tid].pc->as<RiscvISA::PCState>();
assert(dbpbtb);
dbpbtb->nonControlSquash(fromCommit->commitInfo[tid].squashedTargetId,
fromCommit->commitInfo[tid].squashedStreamId, nc_pc,
dbpbtb->nonControlSquash(fromCommit->commitInfo[tid].squashedTargetId, nc_pc,
0, tid, fromCommit->commitInfo[tid].squashedLoopIter);
} else {
DPRINTF(Fetch, "Dont squash dbq because no meaningful stream\n");
Expand All @@ -1643,7 +1639,7 @@ Fetch::handleDecodeSquash(ThreadID tid)
const auto next_pc =
fromDecode->decodeInfo[tid].nextPC->as<RiscvISA::PCState>();
dbpbtb->controlSquash(
mispred_inst->getFtqId(), mispred_inst->getFsqId(),
mispred_inst->getFtqId(),
mispred_inst->pcState(),
next_pc,
mispred_inst->staticInst, mispred_inst->getInstBytes(),
Expand Down Expand Up @@ -1703,11 +1699,9 @@ Fetch::buildInst(ThreadID tid, StaticInstPtr staticInst,
DPRINTF(Fetch, "Is nop: %i, is move: %i\n", instruction->isNop(),
instruction->isMov());
assert(dbpbtb);
DPRINTF(DecoupleBP, "Set instruction %lu with stream id %lu, fetch id %lu\n",
instruction->seqNum, dbpbtb->fsqHeadId(),
dbpbtb->fsqHeadFtqId());
instruction->setFsqId(dbpbtb->fsqHeadId());
instruction->setFtqId(dbpbtb->fsqHeadFtqId());
DPRINTF(DecoupleBP, "Set instruction %lu with fetch id %lu\n",
instruction->seqNum, dbpbtb->ftqHeadId());
instruction->setFtqId(dbpbtb->ftqHeadId());

#if TRACING_ON
if (trace) {
Expand Down Expand Up @@ -1763,7 +1757,7 @@ bool
Fetch::checkDecoupledFrontend(ThreadID tid)
{
assert(dbpbtb);
if (!isTraceMode() && !dbpbtb->fsqHasHead()) {
if (!isTraceMode() && !dbpbtb->ftqHasHead()) {
dbpbtb->addFtqNotValid();
DPRINTF(Fetch, "Skip fetch when FSQ head is not available\n");
setAllFetchStalls(StallReason::FTQBubble);
Expand Down Expand Up @@ -1991,7 +1985,7 @@ Fetch::performInstructionFetch(ThreadID tid)
// For decoupled frontend (including trace mode), check FTQ availability
StallReason stall = StallReason::NoStall;
while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize &&
!predictedBranch && !fsqEmpty() && !waitForVsetvl) {
!predictedBranch && !ftqEmpty() && !waitForVsetvl) {

// Check memory needs and supply bytes to decoder if required
stall = checkMemoryNeeds(tid, pc_state, curMacroop);
Expand Down Expand Up @@ -2051,13 +2045,13 @@ Fetch::sendNextCacheRequest(ThreadID tid, const PCStateBase &pc_state) {
return;
}

if (fsqEmpty()) {
if (ftqEmpty()) {
DPRINTF(Fetch, "[tid:%i] No FSQ entry available for next fetch\n", tid);
return;
}

assert(dbpbtb);
const auto &stream = dbpbtb->fsqHead();
const auto &stream = dbpbtb->ftqHead();
const Addr start_pc = stream.startPC;
fetchBuffer[tid].startPC = start_pc;

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/o3/fetch.hh
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Expand Up @@ -968,7 +968,7 @@ class Fetch

// Decoupled+BTB-only: fetch consumes the supplying FSQ entry directly.
// If no head is available, fetch stalls (no extra "supply" state machine).
bool fsqEmpty() const { return !dbpbtb || !dbpbtb->fsqHasHead(); }
bool ftqEmpty() const { return !dbpbtb || !dbpbtb->ftqHasHead(); }

// Number of dynamic instructions fetched within the current FTQ entry.
// Used to explicitly notify the BPU when an entry is consumed (Phase5 prep).
Expand Down
10 changes: 3 additions & 7 deletions src/cpu/o3/iew.cc
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Expand Up @@ -567,7 +567,6 @@ IEW::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->squashedStreamId[tid] = inst->getFsqId();
toCommit->squashedTargetId[tid] = inst->getFtqId();
toCommit->squashedLoopIter[tid] = inst->getLoopIteration();
toCommit->branchTaken[tid] = inst->pcState().branching();
Expand All @@ -581,10 +580,9 @@ IEW::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
wroteToTimeBuffer = true;

DPRINTF(DecoupleBP,
"Branch misprediction (pc=%#lx) set stream id to %lu, target "
"Branch misprediction (pc=%#lx) set target "
"id to %lu, loop iter to %u\n",
toCommit->pc[tid]->instAddr(),
toCommit->squashedStreamId[tid],
toCommit->squashedTargetId[tid],
toCommit->squashedLoopIter[tid]);
}
Expand All @@ -607,7 +605,6 @@ IEW::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
toCommit->squash[tid] = true;

toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->squashedStreamId[tid] = inst->getFsqId();
toCommit->squashedTargetId[tid] = inst->getFtqId();
toCommit->squashedLoopIter[tid] = inst->getLoopIteration();
set(toCommit->pc[tid], inst->pcState());
Expand All @@ -619,10 +616,9 @@ IEW::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
wroteToTimeBuffer = true;

DPRINTF(DecoupleBP,
"Memory violation (pc=%#lx) set stream id to %lu, target id "
"Memory violation (pc=%#lx) set target id "
"to %lu, loop iter to %u\n",
toCommit->pc[tid]->instAddr(),
toCommit->squashedStreamId[tid],
toCommit->squashedTargetId[tid],
toCommit->squashedLoopIter[tid]);

Expand Down Expand Up @@ -1570,7 +1566,7 @@ IEW::SquashCheckAfterExe(DynInstPtr inst)
if (inst->isControl()) {
auto &resolved_cfis = toFetch->iewInfo[tid].resolvedCFIs;
TimeStruct::IewComm::ResolvedCFIEntry entry;
entry.fsqId = inst->getFsqId();
entry.ftqId = inst->getFtqId();
entry.pc = inst->getPC();
resolved_cfis.push_back(entry);
}
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/o3/trace/TraceFetch.cc
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Expand Up @@ -536,8 +536,8 @@ TraceFetch::chooseWrongPathNopSize(ThreadID tid, Addr pc)
bool taken = false;
if (fetch.isBTBPred()) {
assert(fetch.dbpbtb);
if (fetch.dbpbtb->fsqHasHead()) {
const auto &stream = fetch.dbpbtb->fsqHead();
if (fetch.dbpbtb->ftqHasHead()) {
const auto &stream = fetch.dbpbtb->ftqHead();
block_end = stream.predEndPC;
taken_pc = stream.predBranchInfo.pc;
taken = stream.predTaken;
Expand Down
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