Skip to content

Utage check rtl align #773

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
CJ362ff wants to merge 43 commits into
base: xs-dev
Choose a base branch
from
Open

Utage check rtl align #773

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
43 commits
Select commit Hold shift + click to select a range
51b7bde
cpu-o3: split microtage out of tage
Jan 6, 2026
b26fdc7
cpu-o3: enhance branch index calculation in MicroTAGE to handle edge …
Jan 6, 2026
8b35681
cpu-o3: update blockWidth calculation to handle zero blockSize
Jan 6, 2026
034f920
cpu-o3: adjust MicroTAGE parameters and clean up code for clarity
Jan 8, 2026
0bb5cd3
cpu-o3: remove unused variable 'usingBasetable'
Jan 8, 2026
82d3253
cpu-o3: MicroTAGE to remove base table and alternative prediction
Jan 9, 2026
d660fb0
cpu-o3: update MicroTAGE parameters for consistency
Jan 9, 2026
b10b621
cpu-o3: remove alternative prediction logic
Jan 12, 2026
076d8f1
cpu-o3: refine MicroTAGE parameters and remove unused variables
Jan 13, 2026
ef6b810
cpu-o3: update MicroTAGE history length parameter to 16
Jan 13, 2026
91b8738
cpu-o3: enhance MicroTAGE history management with ahead queues
Jan 14, 2026
3df7a28
cpu-o3:open microtage
Jan 15, 2026
06ff70a
cpu-o3:close utage in ideal
Jan 15, 2026
5a20e0f
cpu-o3: update folded history queue size limit
Jan 23, 2026
2aefbfc
cpu-o3: disable MicroTAGE in branch prediction configuration
Jan 23, 2026
90819cc
cpu-o3: refine folded history queue management in doUpdateHist
Jan 23, 2026
7e1a7f0
cpu-o3: update .gitignore and modify MicroTAGE predictor includes
Jan 28, 2026
54ef187
cpu-o3: refactor MicroTAGE history management by removing ahead index…
Jan 28, 2026
e376c5a
cpu-o3: disable MicroTAGE predictor in setKmhV3Ideal
Jan 29, 2026
6d4ce57
cpu-o3: enhance MicroTAGE predictor to support alternative tag history
Jan 29, 2026
fdd6fa0
cpu-o3:enable utage in idael
Jan 29, 2026
1e5927f
cpu-o3: remove alternative tag history from MicroTAGE index
Jan 29, 2026
d87766d
cpu-o3: implement ahead index history management in MicroTAGE
Jan 30, 2026
9f9bf9c
cpu-o3: add debug logging in MicroTAGE updates
Feb 2, 2026
98ad6f0
cpu-o3: update index folded history recovery in MicroTAGE
Mar 3, 2026
bda309c
cpu-o3: update doUpdateHist to handle ahead index folded history
Mar 3, 2026
83f8450
cpu-o3: enhance ahead index history management in MicroTAGE
Mar 4, 2026
1ce1612
cpu: Add UTAGE flag and clean up MicroTAGE
Mar 4, 2026
17bba15
cpu-o3: correct invalidation logic for duplicated entries in AheadBTB
Mar 5, 2026
b17f4d8
cpu-o3: update uTAGE parameters *4 for improved configuration
Mar 5, 2026
66f118a
cpu-o3: fix invalidation logic for duplicated entries in AheadBTB
Mar 5, 2026
13205b5
cpu-o3: refine MicroTAGE parameters for improved configuration
Mar 5, 2026
d3387c2
cpu-o3: update MicroTAGE parameters for improved configuration
Mar 5, 2026
fcd94e7
cpu-o3: update MicroTAGE history lengths for improved accuracy
Mar 5, 2026
35f0f11
cpu-o3: tune MicroTAGE params and fix folded hist check
Mar 5, 2026
6ef6dec
cpu-o3: Tune uTAGE defaults and ignore spec06 outputs
Mar 6, 2026
8b77a25
util: Revert spec06 ignore pattern
Mar 6, 2026
55c5f1a
cpu-o3: Remove unused includes
Mar 6, 2026
9e6be62
cpu-o3: Use FetchTarget in MicroTAGE interfaces
Mar 6, 2026
8c18550
cpu-o3: useful bit handling in uTAGE to use a 2-bit counter
Mar 6, 2026
8d5b2a9
cpu-o3: change tage longth to 15 15 16 16
Mar 9, 2026
d6de129
cpu-o3: aligin utage history longth
Mar 9, 2026
b89e3d1
cpu-o3 :back to normal
Mar 10, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions configs/example/idealkmhv3.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,7 @@ def setKmhV3IdealParams(args, system):
if args.bp_type == 'DecoupledBPUWithBTB':
cpu.branchPred.ftq_size = 64
cpu.branchPred.fsq_size = 64
# cpu.branchPred.microtage.enabled = False

# l1 cache per core
if args.caches:
Expand Down
2 changes: 1 addition & 1 deletion configs/example/kmhv3.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ def setKmhV3Params(args, system):

cpu.branchPred.ubtb.enabled = True
cpu.branchPred.abtb.enabled = True
cpu.branchPred.microtage.enabled = False
cpu.branchPred.microtage.enabled = True
cpu.branchPred.mbtb.enabled = True
cpu.branchPred.tage.enabled = True
cpu.branchPred.ittage.enabled = True
Expand Down
37 changes: 27 additions & 10 deletions src/cpu/pred/BranchPredictor.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1060,16 +1060,33 @@ class BTBTAGE(TimedBaseBTBPredictor):
enableBankConflict = Param.Bool(False, "Enable bank conflict simulation")
numDelay = 2

class MicroTAGE(BTBTAGE):
"""A smaller TAGE predictor configuration to assist uBTB"""
enableSC = Param.Bool(False, "Enable SC or not") # TODO: BTBTAGE doesn't support SC
numPredictors = 1
tableSizes = [512]
TTagBitSizes = [16]
TTagPcShifts = [1]
class MicroTAGE(TimedBaseBTBPredictor):
"""Micro-sized BTB TAGE predictor used alongside uBTB"""
type = 'MicroTAGE'
cxx_class = 'gem5::branch_prediction::btb_pred::MicroTAGE'
cxx_header = "cpu/pred/btb/microtage.hh"

needMoreHistories = Param.Bool(True, "MicroTAGE needs more histories")
enableSC = Param.Bool(False, "Enable SC or not")
updateOnRead = Param.Bool(True,"Enable update on read, no need to save tage meta in FTQ")
# Keep vector parameters consistent with numPredictors to avoid constructor asserts.
numPredictors = Param.Unsigned(4, "Number of TAGE predictors")
tableSizes = VectorParam.Unsigned([512],"the TAGE T0~Tn length")
TTagBitSizes = VectorParam.Unsigned([16],"the T0~Tn entry's tag bit size")
TTagPcShifts = VectorParam.Unsigned([1] ,"when the T0~Tn entry's tag generating, PC right shift")
blockSize = Param.Unsigned(32,"tage index function uses 32B aligned block address")

histLengths = [16]
numDelay = 0
histLengths = VectorParam.Unsigned([16] ,"the BTB TAGE T0~Tn history length")
Comment on lines +1072 to +1079
Copy link
Copy Markdown

@coderabbitai coderabbitai bot Mar 10, 2026

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ Potential issue | 🔴 Critical

🧩 Analysis chain

🏁 Script executed:

#!/bin/bash
# Description: Search for MicroTAGE constructor and check how it uses these vector parameters

# Find the MicroTAGE implementation
fd -e cc -e cpp -e hh -e hpp microtage --exec cat {} \; 2>/dev/null | head -200

# Also check BTBTAGE for comparison on how vectors are used
rg -n -A 10 'tableSizes|TTagBitSizes|histLengths' --type cpp -g '*btb_tage*'

Repository: OpenXiangShan/GEM5

Length of output: 13355

🏁 Script executed:

# Check the MicroTAGE class definition in BranchPredictor.py
sed -n '1063,1089p' src/cpu/pred/BranchPredictor.py

Repository: OpenXiangShan/GEM5

Length of output: 1827

Vector parameter sizes do not match numPredictors—fix required to avoid runtime assertion failure.

The C++ constructor checks that all vector parameters have size >= numPredictors. Currently, numPredictors = 4 but all vector parameters (tableSizes, TTagBitSizes, TTagPcShifts, histLengths) have only 1 element. This will trigger assertion failures at lines 109, 118, 120, and 123 of src/cpu/pred/btb/btb_tage.cc.

Each vector must be expanded to have 4 elements. For reference, BTBTAGE (lines 1043-1052) correctly defines all vectors with 8 elements matching its numPredictors = 8.

Proposed fix 
     # Keep vector parameters consistent with numPredictors to avoid constructor asserts.
     numPredictors = Param.Unsigned(4, "Number of TAGE predictors")
-    tableSizes = VectorParam.Unsigned([512],"the TAGE T0~Tn length")
-    TTagBitSizes = VectorParam.Unsigned([16],"the T0~Tn entry's tag bit size")
-    TTagPcShifts = VectorParam.Unsigned([1] ,"when the T0~Tn entry's tag generating, PC right shift")
+    tableSizes = VectorParam.Unsigned([512]*4,"the TAGE T0~Tn length")
+    TTagBitSizes = VectorParam.Unsigned([16]*4,"the T0~Tn entry's tag bit size")
+    TTagPcShifts = VectorParam.Unsigned([1]*4,"when the T0~Tn entry's tag generating, PC right shift")
     blockSize = Param.Unsigned(32,"tage index function uses 32B aligned block address")

-    histLengths = VectorParam.Unsigned([16]  ,"the BTB TAGE T0~Tn history length")
+    histLengths = VectorParam.Unsigned([4, 8, 13, 16],"the BTB TAGE T0~Tn history length")

The histLengths values are illustrative. Use history lengths appropriate for the MicroTAGE design (typically geometrically increasing, e.g., multiples of 4).

🧰 Tools
🪛 Ruff (0.15.5)

[error] 1073-1073: Param may be undefined, or defined from star imports

(F405)

[error] 1074-1074: VectorParam may be undefined, or defined from star imports

(F405)

[error] 1075-1075: VectorParam may be undefined, or defined from star imports

(F405)

[error] 1076-1076: VectorParam may be undefined, or defined from star imports

(F405)

[error] 1077-1077: Param may be undefined, or defined from star imports

(F405)

[error] 1079-1079: VectorParam may be undefined, or defined from star imports

(F405)

🤖 Prompt for AI Agents 
Verify each finding against the current code and only fix it if needed.

In `@src/cpu/pred/BranchPredictor.py` around lines 1072 - 1079, The vector params
tableSizes, TTagBitSizes, TTagPcShifts, and histLengths currently have only one
element while numPredictors is 4, which will trigger constructor assertions;
update each VectorParam (tableSizes, TTagBitSizes, TTagPcShifts, histLengths) to
contain 4 entries to match numPredictors (e.g., expand values from a
single-element list to four appropriate entries), and for histLengths use a
geometrically increasing sequence suitable for MicroTAGE (e.g., multiples of 4)
so sizes are consistent with the BTBTAGE-style definitions and avoid runtime
failures.

maxHistLen = Param.Unsigned(970,"The length of history passed from DBP")
numTablesToAlloc = Param.Unsigned(1,"The number of table to allocated each time")
numWays = Param.Unsigned(2, "Number of ways per set")
baseTableSize = Param.Unsigned(256,"Base table size")
maxBranchPositions = Param.Unsigned(32,"Maximum branch positions per 64-byte block")
useAltOnNaSize = Param.Unsigned(128,"Size of the useAltOnNa table")
useAltOnNaWidth = Param.Unsigned(7,"Width of the useAltOnNa table")
numBanks = Param.Unsigned(4,"Number of banks for bank conflict simulation")
enableBankConflict = Param.Bool(False,"Enable bank conflict simulation")
numDelay = Param.Unsigned(0,"Prediction latency in cycles")

class BTBITTAGE(TimedBaseBTBPredictor):
type = 'BTBITTAGE'
Expand Down Expand Up @@ -1170,7 +1187,7 @@ class DecoupledBPUWithBTB(BranchPredictor):
numStages = Param.Unsigned(4, "Maximum number of stages in the pipeline")
ubtb = Param.UBTB(UBTB(), "UBTB predictor")
abtb = Param.AheadBTB(AheadBTB(), "ABTB predictor")
microtage = Param.BTBTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
microtage = Param.MicroTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
mbtb = Param.MBTB(MBTB(), "MBTB predictor")
tage = Param.BTBTAGE(BTBTAGE(), "TAGE predictor")
ittage = Param.BTBITTAGE(BTBITTAGE(), "ITTAGE predictor")
Expand Down
5 changes: 4 additions & 1 deletion src/cpu/pred/SConscript
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,8 @@ SimObject('BranchPredictor.py', sim_objects=[
'DecoupledStreamBPU', 'DefaultFTB', 'DecoupledBPUWithFTB',
'TimedBaseFTBPredictor', 'FTBTAGE', 'FTBRAS', 'FTBuRAS', 'FTBITTAGE',
'AheadBTB', 'MBTB', 'UBTB', 'DecoupledBPUWithBTB',
'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])
'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'MicroTAGE',
'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])

DebugFlag('Indirect')
Source('bpred_unit.cc')
Expand Down Expand Up @@ -100,6 +101,7 @@ Source('btb/abtb.cc')
Source('btb/mbtb.cc')
Source('btb/timed_base_pred.cc')
Source('btb/btb_tage.cc')
Source('btb/microtage.cc')
Source('btb/btb_ittage.cc')
Source('btb/btb_mgsc.cc')
Source('btb/folded_hist.cc')
Expand All @@ -125,6 +127,7 @@ DebugFlag('FTB')
DebugFlag('TAGE')
DebugFlag('TAGEUseful')
DebugFlag('TAGEHistory')
DebugFlag('UTAGE')
DebugFlag('ITTAGE')
DebugFlag('ITTAGEHistory')
DebugFlag('FoldedHist')
Expand Down
3 changes: 2 additions & 1 deletion src/cpu/pred/btb/decoupled_bpred.hh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
#include "cpu/pred/btb/btb_tage.hh"
#include "cpu/pred/btb/btb_ubtb.hh"
#include "cpu/pred/btb/mbtb.hh"
#include "cpu/pred/btb/microtage.hh"
#include "cpu/pred/btb/ras.hh"
#include "cpu/pred/general_arch_db.hh"

Expand Down Expand Up @@ -81,7 +82,7 @@ class DecoupledBPUWithBTB : public BPredUnit
UBTB *ubtb{};
AheadBTB *abtb{};
MBTB *mbtb{};
BTBTAGE *microtage{};
MicroTAGE *microtage{};
BTBTAGE *tage{};
BTBITTAGE *ittage{};
BTBMGSC *mgsc{};
Expand Down
Loading
Loading
⚡