fix(MMIOBridge): modify TIMERRange from fix value to soc parameter (OpenXiangShan#453)

* fix(MMIOBridge): modify TIMERRange from fix value to soc parameter

* chore(L2Param): add comment

* chore(MMIOBridge): optimize refer to pr comment

* chore(L2Param): optimize refer to pr comment

Author: zhaohong1988

src/main/scala/coupledL2/CoupledL2.scala

@@ -41,7 +41,7 @@ trait HasCoupledL2Parameters {
   def enableCHI = p(EnableCHI)
   def enableClockGate = p(EnableL2ClockGate)
   def cacheParams = p(L2ParamKey)
-  def EnablePrivateClint = cacheParams.EnablePrivateClint
+  def PrivateClintRange = cacheParams.PrivateClintRange
 
   def XLEN = 64
   def blocks = cacheParams.sets * cacheParams.ways

src/main/scala/coupledL2/L2Param.scala

@@ -19,13 +19,13 @@ package coupledL2
 
 import chisel3._
 import chisel3.util.log2Ceil
-import freechips.rocketchip.diplomacy.{BufferParams, AddressSet}
+import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import org.chipsalliance.cde.config.Field
 import huancun.{AliasKey, CacheParameters, IsHitKey, PrefetchKey}
 import coupledL2.prefetch._
-import utility.{MemReqSource, ReqSourceKey, Code}
+import utility.{Code, MemReqSource, ReqSourceKey}
 
 case object EnableCHI extends Field[Boolean](false)
 case object EnableL2ClockGate extends Field[Boolean](true)
@@ -132,8 +132,8 @@ case class L2Param(
   hasMbist: Boolean = false,
   hasSramCtl: Boolean = false,
 
-  // Enable new clint
-  EnablePrivateClint: Boolean = false
+  // both EnablePrivateClint and PrivateClintRange are from soc parameters.
+  PrivateClintRange: Option[AddressSet] = None
 ) {
   def toCacheParams: CacheParameters = CacheParameters(
     name = name,

src/main/scala/coupledL2/tl2chi/MMIOBridge.scala

@@ -38,16 +38,16 @@ class MMIOBridge()(implicit p: Parameters) extends LazyModule
     * MMIO node
     */
   val beuRange = AddressSet(0x38010000, 4096 - 1)
-  val clintRange = AddressSet(0x38000000L, 0xFFFF)
-  val peripheralRange = if (!EnablePrivateClint) { // clint is interated with periph bus
-    AddressSet(
-      0x0, 0xffffffffffffL
-    ).subtract(beuRange)
-  } else {
-    AddressSet(
-      0x0, 0xffffffffffffL
-    ).subtract(beuRange).flatMap(_.subtract(clintRange))
-  }
+  val clintRange = PrivateClintRange
+  // clint is interated with periph bus
+  val peripheralRange =
+    AddressSet(0x0, 0xffffffffffffL).subtract(beuRange).flatMap {
+      addrSet =>
+        clintRange match {
+          case Some(cRange) => addrSet.subtract(cRange)
+          case None => Seq(addrSet)
+        }
+    }
 
   val mmioNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
     managers = Seq(TLSlaveParameters.v1(