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feat(OpenLLC): add support for ReadNoSnp transaction #22

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Merged
sumailyyc merged 1 commit into from
Dec 16, 2024
Merged

feat(OpenLLC): add support for ReadNoSnp transaction #22

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12 changes: 7 additions & 5 deletions src/main/scala/openLLC/MainPipe.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -126,9 +126,10 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
val cleanInvalid_s3 = !refill_task_s3 && opcode_s3 === CleanInvalid
val cleanShared_s3 = !refill_task_s3 && opcode_s3 === CleanShared
val writeCleanFull_s3 = !refill_task_s3 && opcode_s3 === WriteCleanFull
val readNoSnp_s3 = !refill_task_s3 && opcode_s3 === ReadNoSnp

assert(!task_s3.valid || refill_task_s3 || readNotSharedDirty_s3 || readUnique_s3 || makeUnique_s3 || writeBackFull_s3 ||
evict_s3 || makeInvalid_s3 || cleanInvalid_s3 || cleanShared_s3 || writeCleanFull_s3, "Unsupported opcode")
evict_s3 || makeInvalid_s3 || cleanInvalid_s3 || cleanShared_s3 || writeCleanFull_s3 || readNoSnp_s3, "Unsupported opcode")

/**
* Requests have different coherence states after processing
Expand Down Expand Up @@ -257,6 +258,7 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
val cleanInvalid_s4 = RegNext(cleanInvalid_s3, false.B)
val cleanShared_s4 = RegNext(cleanShared_s3, false.B)
val writeCleanFull_s4 = RegNext(writeCleanFull_s3, false.B)
val readNoSnp_s4 = RegNext(readNoSnp_s3, false.B)
val sharedReq_s4 = RegNext(sharedReq_s3, false.B)
val exclusiveReq_s4 = RegNext(exclusiveReq_s3, false.B)
val releaseReq_s4 = RegNext(releaseReq_s3, false.B)
Expand Down Expand Up @@ -374,7 +376,7 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
val respSC_s4 = sharedReq_s4
val respUC_s4 = makeUnique_s4 || !makeUnique_s4 && exclusiveReq_s4 && (!selfDirty_s4 || !self_hit_s4)
val respUD_s4 = !makeUnique_s4 && exclusiveReq_s4 && self_hit_s4 && selfDirty_s4
val respI_s4 = releaseReq_s4 || invalidReq_s4 || cleanReq_s4 || writeCleanFull_s4
val respI_s4 = releaseReq_s4 || invalidReq_s4 || cleanReq_s4 || writeCleanFull_s4 || readNoSnp_s4
val snpVec_comp_s4 = VecInit(
Mux(
request_snoop_s4,
Expand All @@ -394,12 +396,12 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
)

comp_s4.valid := task_s4.valid && (
releaseReq_s4 || invalidReq_s4 || cleanReq_s4 || makeUnique_s4 || writeCleanFull_s4 ||
releaseReq_s4 || invalidReq_s4 || cleanReq_s4 || makeUnique_s4 || writeCleanFull_s4 || readNoSnp_s4 ||
(readNotSharedDirty_s4 || readUnique_s4) && !self_hit_s4
)
comp_s4.bits.state.s_comp := false.B
comp_s4.bits.state.s_urgentRead := true.B
comp_s4.bits.state.w_datRsp := !(readNotSharedDirty_s4 || readUnique_s4)
comp_s4.bits.state.w_datRsp := !(readNotSharedDirty_s4 || readUnique_s4 || readNoSnp_s4)
comp_s4.bits.state.w_snpRsp := !Cat(snpVec_comp_s4).orR
comp_s4.bits.state.w_compack := !(readUnique_s4 || readNotSharedDirty_s4 || makeUnique_s4)
comp_s4.bits.state.w_comp := !(cleanInvalid_s4 && self_hit_s4 && selfDirty_s4)
Expand All @@ -420,7 +422,7 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
mem_task_s4.expCompAck := false.B

// need ReadNoSnp/WriteNoSnp downwards
val memRead_s4 = (readNotSharedDirty_s4 || readUnique_s4) && !self_hit_s4 && !peerRNs_hit_s4
val memRead_s4 = (readNotSharedDirty_s4 || readUnique_s4) && !self_hit_s4 && !peerRNs_hit_s4 || readNoSnp_s4
val memWrite_s4 = cleanReq_s4 && unique_peerRN_s4 || writeCleanFull_s4
mem_s4.valid := task_s4.valid && (memRead_s4 || memWrite_s4)
mem_s4.bits.state.s_issueReq := false.B
Expand Down
3 changes: 2 additions & 1 deletion src/main/scala/openLLC/RequestArb.scala
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Expand Up @@ -67,8 +67,9 @@ class RequestArb(implicit p: Parameters) extends LLCModule with HasClientInfo wi
val isCleanInvalid_s1 = !task_s1.bits.refillTask && task_s1.bits.chiOpcode === CleanInvalid
val isCleanShared_s1 = !task_s1.bits.refillTask && task_s1.bits.chiOpcode === CleanShared
val isWriteCleanFull_s1 = !task_s1.bits.refillTask && task_s1.bits.chiOpcode === WriteCleanFull
val isReadNoSnp_s1 = !task_s1.bits.refillTask && task_s1.bits.chiOpcode === ReadNoSnp

val isRead_s1 = isReadNotSharedDirty_s1 || isReadUnique_s1
val isRead_s1 = isReadNotSharedDirty_s1 || isReadUnique_s1 || isReadNoSnp_s1
val isClean_s1 = isCleanInvalid_s1 || isCleanShared_s1 || isWriteCleanFull_s1

// To prevent data hazards caused by read-after-write conflicts in the directory,
Expand Down
3 changes: 2 additions & 1 deletion src/main/scala/openLLC/ResponseUnit.scala
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Expand Up @@ -265,7 +265,8 @@ class ResponseUnit(implicit p: Parameters) extends LLCModule with HasCHIOpcodes
}

/* Issue */
val isRead = buffer.map(e => e.task.chiOpcode === ReadUnique || e.task.chiOpcode === ReadNotSharedDirty)
val isRead = buffer.map(e => e.task.chiOpcode === ReadUnique || e.task.chiOpcode === ReadNotSharedDirty ||
e.task.chiOpcode === ReadNoSnp)
txdatArb.io.in.zip(buffer).zip(isRead).foreach { case ((in, e), r) =>
in.valid := e.valid && e.state.w_datRsp && e.state.w_snpRsp && e.state.s_urgentRead && !e.state.s_comp && r
in.bits.task := e.task
Expand Down
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