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5 changes: 3 additions & 2 deletions src/main/scala/openLLC/utils/OpenNCB.scala
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.amba.axi4.AXI4Parameters._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
import coupledL2.L2ParamKey
import coupledL2.tl2chi._
import cc.xiangshan.openncb._
import cc.xiangshan.openncb.axi._
Expand Down Expand Up @@ -80,8 +81,8 @@ class OpenNCBImp(wrapper: OpenNCB)(implicit p: Parameters) extends LazyModuleImp
reqRsvdcWidth = REQ_RSVDC_WIDTH,
datRsvdcWidth = DAT_RSVDC_WIDTH,
dataWidth = DATA_WIDTH,
dataCheckPresent = true,
poisonPresent = true,
dataCheckPresent = DATACHECK_WIDTH != 0,
poisonPresent = POISON_WIDTH != 0,
mpamPresent = true
)
case NCBParametersKey => ncbParams
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3 changes: 2 additions & 1 deletion src/test/scala/TestTop.scala
Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,8 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue:
readCompDMT = false,
writeCancelable = false,
writeNoError = true,
axiBurstAlwaysIncr = true
axiBurstAlwaysIncr = true,
chiDataCheck = EnumCHIDataCheck.OddParity
)
})))

Expand Down