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feat(LLCParam): fix parseAddress in case PAddrBits > CHI Addr width #60

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Merged
linjuanZ merged 1 commit into from
Apr 22, 2025
Merged

feat(LLCParam): fix parseAddress in case PAddrBits > CHI Addr width #60

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3 changes: 2 additions & 1 deletion src/main/scala/openLLC/LLCParam.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Field, Parameters}
import coupledL2.L2Param
import huancun.CacheParameters
import utility.ZeroExt

case class ResourceConfig(refill: Int, response: Int, snoop: Int, memory: Int)

Expand Down Expand Up @@ -99,7 +100,7 @@ trait HasOpenLLCParameters {
val bank = offset >> offsetBits
val set = bank >> bankBits
val tag = set >> setBits
(tag(tagBits - 1, 0), set(setBits - 1, 0), if (bankBits == 0) 0.U(0.W) else bank(bankBits - 1, 0),
(ZeroExt(tag, tagBits), set(setBits - 1, 0), if (bankBits == 0) 0.U(0.W) else bank(bankBits - 1, 0),
offset(offsetBits - 1, 0))
}

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