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difftest: pipeline FPGA batch bus + beat-serialize AXIS to ease conge… #3086

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This workflow is awaiting approval from a maintainer in #847

Triggered via pull request April 10, 2026 10:47

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synchronize #847

difftest-fpga-timing-20260402

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This workflow is awaiting approval from a maintainer in #847

main.yml

on: pull_request

test-difftest-main

test-gsim-rocketchip

test-fpga-nutshell

test-vcs-top-nutshell

test-verilator-nutshell

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