difftest: pipeline FPGA batch bus + beat-serialize AXIS to ease conge…#847
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difftest: pipeline FPGA batch bus + beat-serialize AXIS to ease conge…#847xiaokamikami wants to merge 2 commits intomasterfrom
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Maybe rebase the master and test again? |
…stion - Cut the wide Gateway->Host path with a register slice to reduce long routes. - Replace 16008-bit per-beat shift with beat-indexed serialization to shrink active cones. - Intended to ease routing congestion and improve PCIe-clock timing.
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@copilot Give a short commit message, like previous commit message in this repo. |
Co-authored-by: klin02 <78006150+klin02@users.noreply.github.com>
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Cut the wide Gateway->Host path with a register slice to reduce long routes.
Replace 16008-bit per-beat shift with beat-indexed serialization to shrink active cones.
Intended to ease routing congestion and improve PCIe-clock timing.