feat(ci): add workflow dispatch for STA timing analysis CI#817
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xiaokamikami wants to merge 2 commits intomasterfrom
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feat(ci): add workflow dispatch for STA timing analysis CI#817xiaokamikami wants to merge 2 commits intomasterfrom
xiaokamikami wants to merge 2 commits intomasterfrom
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klin02
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| # 12:00 UTC == 20:00 UTC+8 | ||
| - cron: '00 12 * * *' | ||
| workflow_dispatch: | ||
| pull_request: |
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Emin017
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| # Set SDC file | ||
| if [ -z "$SDC_FILE" ]; then | ||
| SDC_FILE="${YOSYS_STA_DIR}/scripts/default.sdc" |
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Note: The default SDC in yosys-sta may not be sufficient for complex processors like XiangShan. If we want a more accurate STA evaluation, we may need to add additional delay constraints on the input and output ports in the SDC.
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We only want to conduct timing analysis on the modules on the diffftest side, in order to ensure that the difftest code can be synthesized on the FPGA.
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