[DRAFT] Add register-only cross-lane reduction for attention#2359

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stefankoncarevic wants to merge 10 commits intoROCm:developfrom

stefankoncarevic:blockwise-reduce-crosslane

Commits on May 4, 2026

Refactor BlockwiseBroadcastReduceOp lowering with DPP support and helper extraction
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Mark gpu::GPUDialect legal in second ConversionTarget and fix Passes.td formatting
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Replace shuffle-based reductions with DPP subgroup reduce for attention kernels
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Updated test
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Remove unused getPerWaveThreadCounts, restore comments and fix indentation in NR-Large-Tree path
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Fix test attributes: use rock.arch/rock.kernel
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Tighten DPP eligibility to require exact thread-count match and use arch DB for wave size
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Drop the escape in canUseDPP.
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Add permlanex16_var cross-lane reduction for partialR=2 on wave32
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Split permlane reduction into SerialPermlane and PR2-Permlane paths for Navi4x
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