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1. packet_handler packet_handler Public

   A verilog design that processes and distributes incoming packets

   HTML

2. processor_design processor_design Public

   This is a simple CPU design using Verilog, for educational purposes

   VHDL

3. RhoDeltaDee/rock-paper-scissors RhoDeltaDee/rock-paper-scissors Public

   A rock-paper-scissors game

   JavaScript

4. VGA_Display_Protocol VGA_Display_Protocol Public

   System Verilog code that displays items through the VGA output of an FPGA.

   SystemVerilog