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Separate instruction and data memories

Status: Open.

#124 In SpinalHDL/VexiiRiscv;

· Rishu31 opened on Apr 2, 2026

Are option "--debug-sysbus=1" and option "--xlen=64" incompatible?

Status: Open.

#123 In SpinalHDL/VexiiRiscv;

· leeguang517 opened on Mar 17, 2026

Adding SDRAM to MicroSoC

Status: Open.

#122 In SpinalHDL/VexiiRiscv;

· RossComputerGuy opened on Mar 15, 2026

MRET causes illegal instruction trap after ECALL in/from M-Mode

Status: Open.

#117 In SpinalHDL/VexiiRiscv;

· Matze584 opened on Feb 12, 2026

Strange CPU Behavior attempting to port from VexRiscv to VexiiRiscv

Status: Open.

#114 In SpinalHDL/VexiiRiscv;

· polymerizedsage opened on Feb 6, 2026

Redundant tracer initialization for harts

Status: Open.

#111 In SpinalHDL/VexiiRiscv;

· ISHKAFEL09 opened on Jan 30, 2026

How to use external JTAG (CMSIS-DAP) with Vexii MicroSoc? (Beginner)

Status: Open.

#105 In SpinalHDL/VexiiRiscv;

· princesuman2004 opened on Jan 9, 2026

Examples for simulate SoC with spi flash?

Status: Open.

#102 In SpinalHDL/VexiiRiscv;

· Jzjerry opened on Dec 22, 2025

There is an inconsistency in mie.LCOFIE

Status: Open.

#96 In SpinalHDL/VexiiRiscv;

· fly-1011 opened on Nov 16, 2025

Trying to connect a LsuL1Cmd port from external units (like CFU) to CPU

Status: Open.

#80 In SpinalHDL/VexiiRiscv;

· Jzjerry opened on Sep 3, 2025

[Feature request] Zmmul extension, no division

Status: Open.

#73 In SpinalHDL/VexiiRiscv;

· jrmoserbaltimore opened on Aug 22, 2025

MicroSoC generation failing with CFU plugin

Status: Open.

#71 In SpinalHDL/VexiiRiscv;

· Rishu31 opened on Aug 20, 2025