feat(support): Add mini opensbi platform support

opensbi-platform/corvus/Kconfig

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+# SPDX-License-Identifier: BSD-2-Clause
+
+#
+# All mandatory drivers or libraries for this platform should
+# be directly selected by the PLATFORM_xyz kconfig symbol.
+#
+# All optional drivers or libraries for this platform should
+# be enabled via configs/defconfig of this platform.
+#
+config PLATFORM_TEMPLATE
+	bool
+	select IPI_MSWI
+	select IRQCHIP_PLIC
+	select SERIAL_UART8250
+	select TIMER_MTIMER
+	default y

opensbi-platform/corvus/README.md

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+This is a mini platform config for opensbi suitble
+for corvus development without dts
+
+Usage:
+In opensbi, `make PLATFORM_DIR=[This dir] FW_PAYLOAD_PATH=[path to rtthread.bin] FW_TEXT_START=0x80000000 FW_PAYLOAD_OFFSET=0x200000 LLVM=[path to toolchains bin]`

opensbi-platform/corvus/objects.mk

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+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+#
+
+# Compiler pre-processor flags
+platform-cppflags-y =
+
+# C Compiler and assembler flags.
+platform-cflags-y =
+platform-asflags-y =
+
+# Linker flags: additional libraries and object files that the platform
+# code needs can be added here
+platform-ldflags-y =
+
+#
+# Command for platform specific "make run"
+# Useful for development and debugging on plaftform simulator (such as QEMU)
+#
+# platform-runcmd = your_platform_run.sh
+
+#
+# Platform RISC-V XLEN, ABI, ISA and Code Model configuration.
+# These are optional parameters but platforms can optionaly provide it.
+# Some of these are guessed based on GCC compiler capabilities
+#
+PLATFORM_RISCV_XLEN = 64
+PLATFORM_RISCV_ABI = lp64
+PLATFORM_RISCV_ISA = rv64ima
+PLATFORM_RISCV_CODE_MODEL = medany
+
+# Space separated list of object file names to be compiled for the platform
+platform-objs-y += platform.o
+
+#
+# If the platform support requires a builtin device tree file, the name of
+# the device tree compiled file should be specified here. The device tree
+# source file be in the form <dt file name>.dts
+#
+# platform-objs-y += <dt file name>.o
+
+# Optional parameter for path to external FDT
+# FW_FDT_PATH="path to platform flattened device tree file"
+
+#
+# Dynamic firmware configuration.
+# Optional parameters are commented out. Uncomment and define these parameters
+# as needed.
+#
+FW_DYNAMIC=y
+
+#
+# Jump firmware configuration.
+# Optional parameters are commented out. Uncomment and define these parameters
+# as needed.
+#
+FW_JUMP=n
+# This needs to be 4MB aligned for 32-bit support
+# This needs to be 2MB aligned for 64-bit support
+# ifeq ($(PLATFORM_RISCV_XLEN), 32)
+# FW_JUMP_OFFSET=0x400000
+# else
+# FW_JUMP_OFFSET=0x200000
+# endif
+# FW_JUMP_FDT_OFFSET=0x2200000
+#
+# You can use fixed address for jump firmware as an alternative option.
+# SBI will prefer "<X>_ADDR" if both "<X>_ADDR" and "<X>_OFFSET" are
+# defined
+# ifeq ($(PLATFORM_RISCV_XLEN), 32)
+# FW_JUMP_ADDR=0x80400000
+# else
+# FW_JUMP_ADDR=0x80200000
+# endif
+# FW_JUMP_FDT_ADDR=0x82200000
+
+#
+# Firmware with payload configuration.
+# Optional parameters are commented out. Uncomment and define these parameters
+# as needed.
+#
+FW_PAYLOAD=y
+# This needs to be 4MB aligned for 32-bit support
+# This needs to be 2MB aligned for 64-bit support
+ifeq ($(PLATFORM_RISCV_XLEN), 32)
+FW_PAYLOAD_OFFSET=0x400000
+else
+FW_PAYLOAD_OFFSET=0x200000
+endif
+# FW_PAYLOAD_ALIGN=0x1000
+# FW_PAYLOAD_PATH="path to next boot stage binary image file"
+# FW_PAYLOAD_FDT_OFFSET=0x2200000
+#
+# You can use fixed address for payload firmware as an alternative option.
+# SBI will prefer "FW_PAYLOAD_FDT_ADDR" if both "FW_PAYLOAD_FDT_OFFSET"
+# and "FW_PAYLOAD_FDT_ADDR" are defined.
+# FW_PAYLOAD_FDT_ADDR=0x82200000

opensbi-platform/corvus/platform.c

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+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ */
+
+#include "sbi/sbi_console.h"
+#include "sbi/sbi_scratch.h"
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_platform.h>
+
+/*
+ * Include these files as needed.
+ * See objects.mk PLATFORM_xxx configuration parameters.
+ */
+#include <sbi_utils/ipi/aclint_mswi.h>
+#include <sbi_utils/irqchip/plic.h>
+#include <sbi_utils/serial/uart8250.h>
+#include <sbi_utils/timer/aclint_mtimer.h>
+
+// Same as baseAddress in StandAlonePLIC
+#define CORVUS_PLIC_ADDR		0x3c000000
+#define CORVUS_PLIC_SIZE		0x4000000
+// Same as extIntrNum in StandAlonePLIC
+#define CORVUS_PLIC_NUM_SOURCES	64
+// Same as p.numSCore + 1 (for master)
+#define CORVUS_HART_COUNT		8
+#define CORVUS_CLINT_ADDR		0x38000000
+#define CORVUS_CLINT_MTIMER_FREQ	1000000
+#define CORVUS_CLINT_MSWI_ADDR	(CORVUS_CLINT_ADDR + \
+					 					CLINT_MSWI_OFFSET)
+// CLINT -> MTIMECMP 
+#define CORVUS_CLINT_MTIMER_ADDR	(CORVUS_CLINT_ADDR + \
+					 					CLINT_MTIMER_OFFSET)
+#define CORVUS_UART_ADDR		0x310b0000
+#define CORVUS_UART_INPUT_FREQ	50000000
+#define CORVUS_UART_BAUDRATE	115200
+#define CORVUS_UART_REGSHIFT    2
+#define CORVUS_UART_REGIOWIDTH  4
+
+static struct plic_data plic = {
+	.addr = CORVUS_PLIC_ADDR,
+	.size = CORVUS_PLIC_SIZE,
+	.num_src = CORVUS_PLIC_NUM_SOURCES,
+	.context_map = {
+		[0] = { 0, 1 },
+		[1] = { 2, 3 },
+		[2] = { 4, 5 },
+		[3] = { 6, 7 },
+		[4] = { 8, 9 },
+		[5] = { 10, 11 },
+		[6] = { 12, 13 },
+		[7] = { 14, 15 },
+	},
+};
+
+
+static struct aclint_mswi_data mswi = {
+	.addr = CORVUS_CLINT_MSWI_ADDR,
+	.size = ACLINT_MSWI_SIZE,
+	.first_hartid = 0,
+	.hart_count = CORVUS_HART_COUNT,
+};
+
+static struct aclint_mtimer_data mtimer = {
+	.mtime_freq = CORVUS_CLINT_MTIMER_FREQ,
+	.mtime_addr = CORVUS_CLINT_MTIMER_ADDR +
+		      ACLINT_DEFAULT_MTIME_OFFSET,
+	.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
+	.mtimecmp_addr = CORVUS_CLINT_MTIMER_ADDR +
+			 ACLINT_DEFAULT_MTIMECMP_OFFSET,
+	.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
+	.first_hartid = 0,
+	.hart_count = CORVUS_HART_COUNT,
+	.has_64bit_mmio = true,
+};
+
+/*
+ * Platform early initialization.
+ */
+static int corvus_early_init(bool cold_boot)
+{
+	int rc;
+
+	if (!cold_boot)
+		return 0;
+
+	rc = uart8250_init(CORVUS_UART_ADDR, CORVUS_UART_INPUT_FREQ,
+			   CORVUS_UART_BAUDRATE, CORVUS_UART_REGSHIFT,
+			   CORVUS_UART_REGIOWIDTH, 0, 0);
+	if (rc)
+		return rc;
+	// Speed up sim
+	sbi_scratch_thishart_ptr()->options = sbi_scratch_thishart_ptr()-> options | SBI_SCRATCH_NO_BOOT_PRINTS;
+	return aclint_mswi_cold_init(&mswi);
+}
+
+/*
+ * Initialize the platform interrupt controller during cold boot.
+ */
+static int corvus_irqchip_init(void)
+{
+	//FIXME: This is problematic. Since every plic thinks it serves HART0
+	return plic_cold_irqchip_init(&plic);
+}
+
+/*
+ * Initialize platform timer during cold boot.
+ */
+static int corvus_timer_init(void)
+{
+	return aclint_mtimer_cold_init(&mtimer, NULL);
+}
+static int corvus_final_init(bool cold_boot){
+	// each HART has a different scratch
+	// we can change the sbi_scratch_thishart_ptr()->next_addr based on
+	// hart id
+	//sbi_printf("\n!!scratch is: %p\n",sbi_scratch_thishart_ptr());
+	return 0;
+}
+
+/*
+ * Platform descriptor.
+ */
+const struct sbi_platform_operations platform_ops = {
+	.early_init	= corvus_early_init,
+	.irqchip_init	= corvus_irqchip_init,
+	.timer_init	= corvus_timer_init,
+	.final_init     = corvus_final_init
+};
+const struct sbi_platform platform = {
+	.opensbi_version	= OPENSBI_VERSION,
+	.platform_version	= SBI_PLATFORM_VERSION(0x0, 0x00),
+	.name			= "Corvus",
+	.features		= SBI_PLATFORM_DEFAULT_FEATURES,
+	.hart_count		= CORVUS_HART_COUNT,
+	.hart_stack_size	= SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
+	.heap_size		= SBI_PLATFORM_DEFAULT_HEAP_SIZE(1),
+	.platform_ops_addr	= (unsigned long)&platform_ops
+};