Hello, when I was using KV260 to reproduce the project, I found that the dfx regions such as pr_0 and pr_1 in Vivado were built as IP instead of Hierarchy. This also caused errors when loading partial.bit and hwh using cpipe.load in Jupyter. How can I solve this problem? Thank you very much
Hello, when I was using KV260 to reproduce the project, I found that the dfx regions such as pr_0 and pr_1 in Vivado were built as IP instead of Hierarchy. This also caused errors when loading partial.bit and hwh using cpipe.load in Jupyter. How can I solve this problem? Thank you very much