🧠 My work focuses on Computer Architecture, TL-Verilog designs, RISC-V systems, and low-level system debugging, particularly analyzing the early boot process of operating systems running on simulated hardware platforms.

⚙️ I actively experiment with TL-Verilog and Makerchip to explore modern hardware design methodologies such as timing-abstract and pipeline-based design.

💻 I work with Verilog and TL-Verilog to build and understand hardware components including pipelines, ALUs, and system-level designs, while exploring their integration with RISC-V processor architectures.

🤖 I have also completed 5+ projects in Artificial Intelligence and Machine Learning, working with Python, data analysis, model training, and applied ML techniques to solve practical problems.

🌱 I’m currently learning RISC-V privilege architecture, QEMU internals, system-level debugging, hardware/software co-design, and advanced computer architecture concepts.

🤝 I’m looking for help with architectural checkpointing techniques and RTL simulation workflows in the OpenPiton ecosystem
https://github.com/PrincetonUniversity/openpiton

📄 IEEE Research Publication: Verilog-based digital hardware design and implementation.
🔗 https://ieeexplore.ieee.org/document/11416567

🚀 My long-term goal is to contribute to open-source processor architectures, hardware design tools, and research in computer architecture.

👨‍💻 All of my projects are available at https://github.com/chillakalyan

📝 I regularly write articles on https://medium.com/@chillakalyan78

💬 Ask me about RISC-V architecture, Linux boot flow, QEMU debugging, GDB analysis, and computer architecture fundamentals

📫 How to reach me chillakalyan78@gmail.com