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Add SAI clock gates, Audio PLL config, and SAI resources in BSP#184

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mciantyre merged 1 commit intomciantyre:masterfrom
tacertain:expose-sai
Mar 10, 2026
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Add SAI clock gates, Audio PLL config, and SAI resources in BSP#184
mciantyre merged 1 commit intomciantyre:masterfrom
tacertain:expose-sai

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Enable SAI1-3 clock gates, configure Audio PLL (PLL4) for 44.1 kHz sample rates, and expose sai1/sai2/sai3 register blocks in board Resources. Addresses issue #182.

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Apparently I still haven't upgraded my rust toolchain!

@tacertain tacertain force-pushed the expose-sai branch 4 times, most recently from 1cf5f2f to 32682aa Compare March 9, 2026 20:08
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OK. I'm done. Ready for review

@mciantyre mciantyre linked an issue Mar 10, 2026 that may be closed by this pull request
Comment thread src/clock_power.rs Outdated
Enable SAI1-3 clock gates, configure Audio PLL (PLL4) for 44.1 kHz
sample rates, and expose sai1/sai2/sai3 register blocks in board Resources.

Update toolchain - fix new clippy errors

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@mciantyre mciantyre merged commit b260eb9 into mciantyre:master Mar 10, 2026
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board::t41() does not expose SAI.

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