Adds PPI support and example#162
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| regs.ch[P::CH].tep.write(|w| unsafe { w.bits(addr) }); | ||
| } | ||
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| fn set_event_endpoint(&mut self, addr: u32) { |
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The manual says that these registers "accept only addresses to registers from the Event/Task group". Does that mean that writing an incorrect address has no effect, or will that cause trouble?
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Hmm, I just tried here on hardware, I used another timer's CC0 register (TIMER1) to see if it would write something to it or hardfault, but nothing happened, no write nor fault, so I guess it just doesn't do anything ?
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I also tried with a RAM address now, same thing.
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It might be really tedious, but we could define an extension trait for all of the events and tasks, it would also let us get rid of the awkward &p.RADIO.tasks_disable as *const _ as u32 dance.
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Awesome! I am keen to try this out! Unfortunately I have little to no experience with the PPI, so I can't really judge about the API ... |
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
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Regarding the "extension trait" idea, here's a quick look for the nrf52832-pac: Events:
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Let me know what you think of https://github.com/thalesfragoso/nrf-hal/pull/1/files, if you like it, I can do all the target gating to get the correct tasks/events for each chip. Right now it (probably) only works on the nrf52832. |
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Looks good! |
* Add extension trait for tasks and events * Easier to maintain structure * Implement other crates, fix regex a bit * That's gross, but it works * Apply suggestions from code review Co-authored-by: Thales <46510852+thalesfragoso@users.noreply.github.com> * Remove nrf9160 impls * More inline always Co-authored-by: Thales <46510852+thalesfragoso@users.noreply.github.com>
This abstraction allows for the usage of PPI channels independently.
I would like an opinion on the
enablemethod, I think that it might have the potential to break an hypothetical abstraction, but probably won't cause any memory safety problems, should we mark it asunsafe?