Add TWIS module

Cargo.toml

@@ -14,6 +14,8 @@ members = [
   "examples/gpiote-demo",
   "examples/wdt-demo",
   "examples/comp-demo",
+  "examples/twim-demo",
+  "examples/twis-demo",
 ]
 
 [profile.dev]

examples/twim-demo/Cargo.toml

@@ -0,0 +1,17 @@
+[package]
+name = "twim-demo"
+version = "0.1.0"
+authors = ["Henrik Alsér"]
+edition = "2018"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+cortex-m = "0.6.2"
+cortex-m-rtic = "0.5.3"
+rtt-target = {version = "0.2.0", features = ["cortex-m"] }
+nrf52840-hal = { features = ["rt"], path = "../../nrf52840-hal" }
+
+[dependencies.embedded-hal]
+version = "0.2.3"
+features = ["unproven"]

examples/twim-demo/Embed.toml

@@ -0,0 +1,46 @@
+[default.probe]
+# The index of the probe in the connected probe list.
+# probe_index = 0
+# The protocol to be used for communicating with the target.
+protocol = "Swd"
+# The speed in kHz of the data link to the target.
+# speed = 1337
+
+[default.flashing]
+# Whether or not the target should be flashed.
+enabled = true
+# Whether or not the target should be halted after flashing.
+halt_afterwards = false
+# Whether or not bytes erased but not rewritten with data from the ELF
+# should be restored with their contents before erasing.
+restore_unwritten_bytes = false
+# The path where an SVG of the assembled flash layout should be written to.
+# flash_layout_output_path = "out.svg"
+
+[default.general]
+# The chip name of the chip to be debugged.
+chip = "nRF52840"
+# A list of chip descriptions to be loaded during runtime.
+chip_descriptions = []
+# The default log level to be used.
+log_level = "Warn"
+
+[default.rtt]
+# Whether or not an RTTUI should be opened after flashing.
+# This is exclusive and cannot be used with GDB at the moment.
+enabled = true
+# A list of channel associations to be displayed. If left empty, all channels are displayed.
+channels = [
+    # { up = 0, down = 0, name = "name" }
+]
+# The duration in ms for which the logger should retry to attach to RTT.
+timeout = 3000
+# Whether timestamps in the RTTUI are enabled
+show_timestamps = true
+
+[default.gdb]
+# Whether or not a GDB server should be opened after flashing.
+# This is exclusive and cannot be used with RTT at the moment.
+enabled = false
+# The connection string in host:port format wher the GDB server will open a socket.
+# gdb_connection_string

examples/twim-demo/src/main.rs

@@ -0,0 +1,127 @@
+#![no_std]
+#![no_main]
+
+use embedded_hal::digital::v2::InputPin;
+use {
+    core::{
+        panic::PanicInfo,
+        sync::atomic::{compiler_fence, Ordering},
+    },
+    hal::{
+        gpio::{p0::Parts, Input, Pin, PullUp},
+        gpiote::Gpiote,
+        pac::TWIM0,
+        twim::*,
+    },
+    nrf52840_hal as hal,
+    rtic::cyccnt::U32Ext,
+    rtt_target::{rprintln, rtt_init_print},
+};
+
+#[rtic::app(device = crate::hal::pac, peripherals = true,  monotonic = rtic::cyccnt::CYCCNT)]
+const APP: () = {
+    struct Resources {
+        twim: Twim<TWIM0>,
+        gpiote: Gpiote,
+        btn1: Pin<Input<PullUp>>,
+        btn2: Pin<Input<PullUp>>,
+        btn3: Pin<Input<PullUp>>,
+        btn4: Pin<Input<PullUp>>,
+    }
+
+    #[init]
+    fn init(mut ctx: init::Context) -> init::LateResources {
+        let _clocks = hal::clocks::Clocks::new(ctx.device.CLOCK).enable_ext_hfosc();
+        ctx.core.DCB.enable_trace();
+        ctx.core.DWT.enable_cycle_counter();
+        rtt_init_print!();
+
+        let p0 = Parts::new(ctx.device.P0);
+        let scl = p0.p0_30.into_floating_input().degrade();
+        let sda = p0.p0_31.into_floating_input().degrade();
+        let btn1 = p0.p0_11.into_pullup_input().degrade();
+        let btn2 = p0.p0_12.into_pullup_input().degrade();
+        let btn3 = p0.p0_24.into_pullup_input().degrade();
+        let btn4 = p0.p0_25.into_pullup_input().degrade();
+
+        let gpiote = Gpiote::new(ctx.device.GPIOTE);
+        gpiote.port().input_pin(&btn1).low();
+        gpiote.port().input_pin(&btn2).low();
+        gpiote.port().input_pin(&btn3).low();
+        gpiote.port().input_pin(&btn4).low();
+        gpiote.port().enable_interrupt();
+
+        let twim = Twim::new(ctx.device.TWIM0, Pins { scl, sda }, Frequency::K100);
+
+        init::LateResources {
+            twim,
+            gpiote,
+            btn1,
+            btn2,
+            btn3,
+            btn4,
+        }
+    }
+
+    #[idle]
+    fn idle(_: idle::Context) -> ! {
+        rprintln!("Press button 1 to READ from addr 0x1A");
+        rprintln!("Press button 2 to WRITE to addr 0x1A");
+        rprintln!("Press button 3 to READ from addr 0x1B");
+        rprintln!("Press button 4 to WRITE from addr 0x1B");
+        loop {
+            cortex_m::asm::wfi();
+        }
+    }
+
+    #[task(binds = GPIOTE, resources = [gpiote], schedule = [debounce])]
+    fn on_gpiote(ctx: on_gpiote::Context) {
+        ctx.resources.gpiote.reset_events();
+        ctx.schedule.debounce(ctx.start + 3_000_000.cycles()).ok();
+    }
+
+    #[task(resources = [twim, gpiote, btn1, btn2, btn3, btn4])]
+    fn debounce(ctx: debounce::Context) {
+        let twim = ctx.resources.twim;
+        if ctx.resources.btn1.is_low().unwrap() {
+            rprintln!("\nREAD from address 0x1A");
+            let rx_buf = &mut [0; 8][..];
+            let res = twim.read(0x1A, rx_buf);
+            rprintln!("Result: {:?}\n{:?}", res, rx_buf);
+        }
+        if ctx.resources.btn2.is_low().unwrap() {
+            rprintln!("\nWRITE to address 0x1A");
+            let mut tx_buf = [0u8; 8];
+            tx_buf.copy_from_slice(&[1, 2, 3, 4, 5, 6, 7, 8]);
+            let res = twim.write(0x1A, &tx_buf[..]);
+            rprintln!("Result: {:?}\n{:?}", res, tx_buf);
+        }
+        if ctx.resources.btn3.is_low().unwrap() {
+            rprintln!("\nREAD from address 0x1B");
+            let rx_buf = &mut [0; 4][..];
+            let res = twim.read(0x1B, rx_buf);
+            rprintln!("Result: {:?}\n{:?}", res, rx_buf);
+        }
+        if ctx.resources.btn4.is_low().unwrap() {
+            rprintln!("\nWRITE to address 0x1B");
+            let mut tx_buf = [0u8; 4];
+            tx_buf.copy_from_slice(&[9, 10, 11, 12]);
+            let res = twim.write(0x1B, &tx_buf[..]);
+            rprintln!("Result: {:?}\n{:?}", res, tx_buf);
+        }
+    }
+
+    extern "C" {
+        fn SWI0_EGU0();
+    }
+};
+
+#[inline(never)]
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    cortex_m::interrupt::disable();
+    rprintln!("{}", info);
+    loop {
+        compiler_fence(Ordering::SeqCst);
+    }
+}

examples/twis-demo/Cargo.toml

@@ -0,0 +1,17 @@
+[package]
+name = "twis-demo"
+version = "0.1.0"
+authors = ["Henrik Alsér"]
+edition = "2018"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+cortex-m = "0.6.2"
+cortex-m-rtic = "0.5.3"
+rtt-target = {version = "0.2.0", features = ["cortex-m"] }
+nrf52840-hal = { features = ["rt"], path = "../../nrf52840-hal" }
+
+[dependencies.embedded-hal]
+version = "0.2.3"
+features = ["unproven"]

examples/twis-demo/Embed.toml

@@ -0,0 +1,46 @@
+[default.probe]
+# The index of the probe in the connected probe list.
+# probe_index = 0
+# The protocol to be used for communicating with the target.
+protocol = "Swd"
+# The speed in kHz of the data link to the target.
+# speed = 1337
+
+[default.flashing]
+# Whether or not the target should be flashed.
+enabled = true
+# Whether or not the target should be halted after flashing.
+halt_afterwards = false
+# Whether or not bytes erased but not rewritten with data from the ELF
+# should be restored with their contents before erasing.
+restore_unwritten_bytes = false
+# The path where an SVG of the assembled flash layout should be written to.
+# flash_layout_output_path = "out.svg"
+
+[default.general]
+# The chip name of the chip to be debugged.
+chip = "nRF52840"
+# A list of chip descriptions to be loaded during runtime.
+chip_descriptions = []
+# The default log level to be used.
+log_level = "Warn"
+
+[default.rtt]
+# Whether or not an RTTUI should be opened after flashing.
+# This is exclusive and cannot be used with GDB at the moment.
+enabled = true
+# A list of channel associations to be displayed. If left empty, all channels are displayed.
+channels = [
+    # { up = 0, down = 0, name = "name" }
+]
+# The duration in ms for which the logger should retry to attach to RTT.
+timeout = 3000
+# Whether timestamps in the RTTUI are enabled
+show_timestamps = true
+
+[default.gdb]
+# Whether or not a GDB server should be opened after flashing.
+# This is exclusive and cannot be used with RTT at the moment.
+enabled = false
+# The connection string in host:port format wher the GDB server will open a socket.
+# gdb_connection_string

examples/twis-demo/src/main.rs

@@ -0,0 +1,120 @@
+#![no_std]
+#![no_main]
+
+use cortex_m::singleton;
+use embedded_hal::digital::v2::OutputPin;
+use {
+    core::{
+        panic::PanicInfo,
+        sync::atomic::{compiler_fence, Ordering},
+    },
+    hal::{
+        gpio::{p0::Parts, Level, Output, Pin, PushPull},
+        pac::TWIS0,
+        twis::*,
+    },
+    nrf52840_hal as hal,
+    rtt_target::{rprintln, rtt_init_print},
+};
+
+const ADDR0: u8 = 0x1A;
+const ADDR1: u8 = 0x1B;
+const BUF0_SZ: usize = 8;
+const BUF1_SZ: usize = 4;
+
+#[rtic::app(device = crate::hal::pac, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        twis: Twis<TWIS0>,
+        buffer0: &'static mut [u8; BUF0_SZ],
+        buffer1: &'static mut [u8; BUF1_SZ],
+        led: Pin<Output<PushPull>>,
+    }
+
+    #[init]
+    fn init(ctx: init::Context) -> init::LateResources {
+        let _clocks = hal::clocks::Clocks::new(ctx.device.CLOCK).enable_ext_hfosc();
+        rtt_init_print!();
+
+        let p0 = Parts::new(ctx.device.P0);
+        let led = p0.p0_06.into_push_pull_output(Level::High).degrade();
+        let scl = p0.p0_14.into_floating_input().degrade();
+        let sda = p0.p0_16.into_floating_input().degrade();
+
+        let twis = Twis::new(ctx.device.TWIS0, Pins { scl, sda }, ADDR0);
+        twis.address1(ADDR1) // Add a secondary i2c address
+            .enable_interrupt(TwiEvent::Write) // Trigger interrupt on WRITE command
+            .enable_interrupt(TwiEvent::Read) // Trigger interrupt on READ command
+            .enable();
+
+        let buffer0 = singleton!(: [u8; BUF0_SZ] = [0; BUF0_SZ]).unwrap();
+        let buffer1 = singleton!(: [u8; BUF1_SZ] = [0; BUF1_SZ]).unwrap();
+        init::LateResources {
+            twis,
+            buffer0,
+            buffer1,
+            led,
+        }
+    }
+
+    #[idle]
+    fn idle(_: idle::Context) -> ! {
+        rprintln!("Waiting for commands from controller...");
+        loop {
+            cortex_m::asm::wfi();
+        }
+    }
+
+    #[task(binds = SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, resources = [twis, buffer0, buffer1, led])]
+    fn on_twis(ctx: on_twis::Context) {
+        let twis = ctx.resources.twis;
+        let buffer0 = ctx.resources.buffer0;
+        let buffer1 = ctx.resources.buffer1;
+        let led = ctx.resources.led;
+
+        if twis.is_event_triggered(TwiEvent::Read) {
+            twis.reset_event(TwiEvent::Read);
+            led.set_low().ok();
+            rprintln!("\nREAD cmd received on addr 0x{:x}", twis.address_match());
+            rprintln!("Writing data to controller...");
+            match twis.address_match() {
+                ADDR0 => {
+                    let res = twis.write(&buffer0[..]);
+                    rprintln!("Result: {:?}\n{:?}", res, buffer0);
+                }
+                ADDR1 => {
+                    let res = twis.write(&buffer1[..]);
+                    rprintln!("Result: {:?}\n{:?}", res, buffer1);
+                }
+                _ => unreachable!(),
+            }
+        }
+        if twis.is_event_triggered(TwiEvent::Write) {
+            twis.reset_event(TwiEvent::Write);
+            led.set_high().ok();
+            rprintln!("\nWRITE cmd received on addr 0x{:x}", twis.address_match());
+            rprintln!("Reading data from controller...");
+            match twis.address_match() {
+                ADDR0 => {
+                    let res = twis.read(&mut buffer0[..]);
+                    rprintln!("Result: {:?}\n{:?}", res, buffer0);
+                }
+                ADDR1 => {
+                    let res = twis.read(&mut buffer1[..]);
+                    rprintln!("Result: {:?}\n{:?}", res, buffer1);
+                }
+                _ => unreachable!(),
+            }
+        }
+    }
+};
+
+#[inline(never)]
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    cortex_m::interrupt::disable();
+    rprintln!("{}", info);
+    loop {
+        compiler_fence(Ordering::SeqCst);
+    }
+}

nrf-hal-common/src/lib.rs

@@ -56,6 +56,8 @@ pub mod timer;
 pub mod twi;
 #[cfg(not(feature = "51"))]
 pub mod twim;
+#[cfg(not(any(feature = "51", feature = "9160")))]
+pub mod twis;
 #[cfg(feature = "51")]
 pub mod uart;
 #[cfg(not(feature = "51"))]