All

40 repositories

netnod-primary-dns-client
Public
Go client for Netnod Primary DNS API
Go
•
BSD 3-Clause "New" or "Revised" License
•0•2•0•1•Updated Apr 23, 2026Apr 23, 2026
dnscontrol
Public
Infrastructure as code for DNS!
Go
•
MIT License
•499•0•0•0•Updated Apr 7, 2026Apr 7, 2026
lego
Public
Let's Encrypt/ACME client and library written in Go
Go
•
MIT License
•1.1k•0•0•0•Updated Mar 12, 2026Mar 12, 2026
nixieclock-NCS314
Public
Enhanced software for the GRA & AFCH NIXIE tube clock
C++
•
Apache License 2.0
•0•1•0•0•Updated Jan 2, 2026Jan 2, 2026
dns-hackathon
Public
Data related to DNS Hackathons
0•2•0•0•Updated Jan 23, 2025Jan 23, 2025
pypeeringmanager
Public
Simple Python client for the Peering-Manager API
Python
•
Apache License 2.0
•3•0•0•0•Updated Mar 29, 2024Mar 29, 2024
vadarklockan
Public
A libray for securely getting time at boot.
C
•
BSD 3-Clause "New" or "Revised" License
•0•5•4•0•Updated Nov 5, 2023Nov 5, 2023
FPGA_NTP_SERVER
Public
A FPGA implementation of the NTP and NTS protocols
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
Other
•16•64•0•1•Updated May 31, 2023May 31, 2023
client_python
Public
Prometheus instrumentation library for Python applications
Python
•
Apache License 2.0
•853•0•0•0•Updated Apr 18, 2023Apr 18, 2023
go-cidrman
Public
golang CIDR block management utilities
Go
•
The Unlicense
•12•3•0•1•Updated Mar 10, 2023Mar 10, 2023
neorv32
Public
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
VHDL
•
BSD 3-Clause "New" or "Revised" License
•324•0•0•0•Updated Mar 2, 2023Mar 2, 2023
nts_noncegen
Public
Nonce generator core written in Verilog
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•1•0•0•Updated Mar 2, 2023Mar 2, 2023
nts
Public
NTS core written in Verilog. This is just a core, see the FPGA_NTP_SERVER project for a complete implementation of the NTS protocol in a FPGA.
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•1•1•0•0•Updated Mar 2, 2023Mar 2, 2023
keymem
Public
Key memory core written in Verilog. Used by the FPGA_NTP_SERVER project
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•2•0•0•Updated Mar 2, 2023Mar 2, 2023
api_extension
Public
api_extension core written in Verilog. Used by the FPGA_NTP_SERVER project
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•1•0•0•Updated Mar 2, 2023Mar 2, 2023
verilog-i2c
Public
Verilog I2C interface for FPGA implementation
Verilog
•
MIT License
•192•0•0•0•Updated Mar 2, 2023Mar 2, 2023
verilog-ethernet
Public
Verilog Ethernet components for FPGA implementation
fpga-ntp-server
fpga-ntp-server
Verilog
•
MIT License
•820•2•0•0•Updated Mar 2, 2023Mar 2, 2023
siphash
Public
SIPHASH core written in Verilog
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•1•0•0•Updated Mar 2, 2023Mar 2, 2023
sha1
Public
SHA1 core written in Verilog. Forked from https://git.cryptech.is/hash/sha1.git/
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•1•0•0•Updated Mar 2, 2023Mar 2, 2023
rosc_entropy
Public
Ring oscillator core written in Verilog. Forked from https://git.cryptech.is/rng/rosc_entropy.git/
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 3-Clause "New" or "Revised" License
•1•6•0•0•Updated Mar 2, 2023Mar 2, 2023
md5
Public
MD5 core written in Verilog
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•3•7•0•0•Updated Mar 2, 2023Mar 2, 2023
cmac
Public
CMAC core written in verilog
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•2•0•0•Updated Mar 2, 2023Mar 2, 2023
aes-siv
Public
AES-SIV core written in Verilog
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•1•0•0•Updated Mar 2, 2023Mar 2, 2023
aes
Public
AES core written in Verilog. Forked from https://git.cryptech.is/cipher/aes.git/
fpga verilog fpga-ntp-server
fpga verilog fpga-ntp-server
Verilog
•
BSD 2-Clause "Simplified" License
•0•1•0•0•Updated Mar 2, 2023Mar 2, 2023
robust-tjanst
Public
kubernetes http security
kubernetes http security ipv6 internet
JavaScript
•
BSD 3-Clause "New" or "Revised" License
•3•23•6•5•Updated Jan 6, 2023Jan 6, 2023
nts-poc-python
Public
NTS proof of concept in Python
nts-poc-python
nts-poc-python
Python
•
Other
•7•10•0•0•Updated Jan 1, 2023Jan 1, 2023
createtables
Public
Creation of tables for IDNA
unicode idna
unicode idna
Ruby
•
BSD 3-Clause "New" or "Revised" License
•2•0•0•1•Updated Oct 6, 2022Oct 6, 2022
base45
Public
Specification of base45 encoding
Java
•4•9•0•0•Updated Jun 15, 2022Jun 15, 2022
draft-faltstrom-unicode12
Public
Source for the draft-faltstrom-unicode11 internet draft
1•0•0•0•Updated Jan 5, 2022Jan 5, 2022
alice-lg
Public
Alice - Through the Looking Glass https://lg-beta.de-cix.net https://lg.ecix.net
Go
•
Other
•51•0•0•0•Updated Nov 15, 2021Nov 15, 2021

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Netnod

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40 repositories

netnod-primary-dns-client

dnscontrol

lego

nixieclock-NCS314

dns-hackathon

pypeeringmanager

vadarklockan

FPGA_NTP_SERVER

client_python

go-cidrman

neorv32

nts_noncegen

nts

keymem

api_extension

verilog-i2c

verilog-ethernet

siphash

sha1

rosc_entropy

md5

cmac

aes-siv

aes

robust-tjanst

nts-poc-python

createtables

base45

draft-faltstrom-unicode12

alice-lg

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Repositories list

40 repositories