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@OpenXiangShan XiangShan

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    94 repositories

    • difftest

      Public
      Modern co-simulation framework for RISC-V CPUs
      C++
      •
      Mulan Permissive Software License, Version 2
      •98•174•7•9•Updated Apr 10, 2026Apr 10, 2026

    • XiangShan

      Public
      Open-source high-performance RISC-V processor
      chiselrisc-vmicroarchitecture
      chiselrisc-vmicroarchitecture
      Scala
      •
      Mulan Permissive Software License, Version 2
      •891•7k•30•132•Updated Apr 10, 2026Apr 10, 2026

    • llvm-project

      Public
      The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
      LLVM
      •
      Other
      •17k•2•0•0•Updated Apr 10, 2026Apr 10, 2026

    • GEM5

      Public
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •72•138•14•63•Updated Apr 10, 2026Apr 10, 2026

    • ready-to-run

      Public
      Shell
      •14•10•3•1•Updated Apr 10, 2026Apr 10, 2026

    • YuQuan

      Public
      Scala
      •
      Mulan Permissive Software License, Version 2
      •11•87•0•0•Updated Apr 10, 2026Apr 10, 2026

    • CoupledL2

      Public
      Open-source non-blocking L2 cache
      Scala
      •
      Other
      •32•57•0•31•Updated Apr 10, 2026Apr 10, 2026

    • tl-test-new

      Public
      The Unified TileLink Memory Subsystem Tester for XiangShan
      C++
      •
      Mulan Permissive Software License, Version 2
      •2•14•0•3•Updated Apr 9, 2026Apr 9, 2026

    • qemu

      Public
      Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs…
      C
      •
      Other
      •6.7k•3•0•3•Updated Apr 9, 2026Apr 9, 2026

    • env-scripts

      Public
      Scripts for XiangShan
      Tcl
      •21•17•0•4•Updated Apr 9, 2026Apr 9, 2026

    • CUTE

      Public
      Scala
      •0•2•1•0•Updated Apr 9, 2026Apr 9, 2026

    • XiangShan-User-Guide

      Public
      The User Guide of XiangShan.
      Markdown
      •
      Creative Commons Attribution 4.0 International
      •9•18•3•1•Updated Apr 9, 2026Apr 9, 2026

    • ChiselAIA

      Public
      RISC-V AIA in Chisel
      chiselriscvinterrupt
      chiselriscvinterruptaia
      Scala
      •
      Mulan Permissive Software License, Version 2
      •4•11•12•2•Updated Apr 8, 2026Apr 8, 2026

    • XSAI

      Public
      A fork of Xiangshan for AI
      Scala
      •
      Mulan Permissive Software License, Version 2
      •891•39•5•0•Updated Apr 8, 2026Apr 8, 2026

    • OpenLLC

      Public
      Scala
      •
      Other
      •12•13•0•4•Updated Apr 7, 2026Apr 7, 2026

    • NEMU

      Public
      Super fast RISC-V ISA emulator for XiangShan processor
      risc-vrisc-v-emulator
      risc-vrisc-v-emulator
      C
      •
      Other
      •126•324•23•15•Updated Apr 7, 2026Apr 7, 2026

    • xs-env

      Public
      XiangShan Frontend Develop Environment
      Shell
      •
      Other
      •69•70•3•1•Updated Apr 3, 2026Apr 3, 2026

    • Utility

      Public
      Scala
      •27•17•0•7•Updated Apr 2, 2026Apr 2, 2026

    • XiangShan-doc

      Public
      Documentation for XiangShan
      Markdown
      •
      Creative Commons Attribution 4.0 International
      •155•434•7•1•Updated Apr 2, 2026Apr 2, 2026

    • gsim

      Public
      C++
      •8•68•1•6•Updated Apr 1, 2026Apr 1, 2026

    • HBL2

      Public
      Open-source non-blocking L2 cache, used in XS-AI system
      Scala
      •
      Other
      •32•3•0•0•Updated Apr 1, 2026Apr 1, 2026

    • CPU2017LiteWrapper

      Public
      Makefile
      •2•3•0•0•Updated Apr 1, 2026Apr 1, 2026

    • CPU2006LiteWrapper

      Public
      Makefile
      •7•14•1•3•Updated Apr 1, 2026Apr 1, 2026

    • HuanCun

      Public
      Open-source high-performance non-blocking cache
      Scala
      •
      Other
      •40•95•2•1•Updated Apr 1, 2026Apr 1, 2026

    • XiangShan-Design-Doc

      Public
      Documentation for XiangShan Design
      Markdown
      •
      Creative Commons Attribution 4.0 International
      •17•48•3•6•Updated Mar 31, 2026Mar 31, 2026

    • rocket-chip

      Public
      Rocket Chip Generator
      Scala
      •
      Other
      •1.2k•8•0•4•Updated Mar 31, 2026Mar 31, 2026

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •664•3•0•0•Updated Mar 27, 2026Mar 27, 2026

    • riscv-linux

      Public
      RISC-V Linux Port
      C
      •
      Other
      •219•6•0•0•Updated Mar 27, 2026Mar 27, 2026

    • gem5_data_proc

      Public
      data preprocessing scripts for gem5 output
      Python
      •19•3•0•0•Updated Mar 26, 2026Mar 26, 2026

    • ChiselIOPMP

      Public
      An open-sourced Chisel implementation of the RISC-V I/O Physical Memory Protection (IOPMP).
      Scala
      •
      Mulan Permissive Software License, Version 2
      •0•2•0•0•Updated Mar 23, 2026Mar 23, 2026
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