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    23 repositories

    • tclwrapper

      Public
      Python wrapper to interact with TCL command line interfaces
      Python
      •
      MIT License
      •7•7•0•0•Updated Mar 25, 2024Mar 25, 2024

    • pyverilator

      Public
      Python wrapper for verilator model
      Python
      •
      MIT License
      •40•94•8•5•Updated Feb 10, 2024Feb 10, 2024

    • parsec

      Public
      C
      •
      Other
      •8•11•0•0•Updated Nov 13, 2020Nov 13, 2020

    • recycle-bsv-lib

      Public
      Collection of BSV packages.
      Bluespec
      •
      MIT License
      •3•8•0•0•Updated Jul 13, 2020Jul 13, 2020

    • riscy-OOO

      Public
      RiscyOO: RISC-V Out-of-Order Processor
      Bluespec
      •
      MIT License
      •28•170•3•0•Updated Jul 3, 2020Jul 3, 2020

    • bluespecrepl

      Public
      Python-based REPL interface for simulating and debugging Bluespec System Verilog
      Python
      •
      MIT License
      •0•3•0•0•Updated Dec 4, 2019Dec 4, 2019

    • RiscyOO_design_doc

      Public
      Design document for RiscyOO processor
      TeX
      •8•5•0•0•Updated Jun 10, 2019Jun 10, 2019

    • gapbs

      Public
      GAP Benchmark Suite
      C++
      •
      Other
      •169•0•0•0•Updated Jun 10, 2019Jun 10, 2019

    • aws-fpga

      Public
      Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
      VHDL
      •
      Other
      •541•1•0•0•Updated Apr 16, 2019Apr 16, 2019

    • coherence

      Public
      Bluespec
      •
      MIT License
      •1•2•0•0•Updated Apr 8, 2019Apr 8, 2019

    • riscy

      Public
      Riscy Processors - Open-Sourced RISC-V Processors
      riscv
      riscv
      Bluespec
      •
      MIT License
      •14•73•1•0•Updated Apr 4, 2019Apr 4, 2019

    • riscv-isa-sim

      Public
      Spike, a RISC-V ISA Simulator
      C
      •
      Other
      •1.1k•0•0•0•Updated Mar 1, 2019Mar 1, 2019

    • riscv-linux

      Public
      RISC-V Linux Port
      C
      •218•0•0•0•Updated Mar 1, 2019Mar 1, 2019

    • connectal

      Public
      Connectal is a framework for software-driven hardware development.
      Bluespec
      •
      MIT License
      •49•0•0•0•Updated Jan 9, 2019Jan 9, 2019

    • riscv-tests

      Public
      C
      •
      Other
      •541•0•0•0•Updated Nov 29, 2018Nov 29, 2018

    • fpgautils

      Public
      Bluespec
      •
      MIT License
      •0•2•0•0•Updated Mar 5, 2018Mar 5, 2018

    • riscv-fesvr

      Public
      RISC-V Frontend Server
      C++
      •
      Other
      •83•0•0•0•Updated Mar 2, 2018Mar 2, 2018

    • riscv-test-env

      Public
      C
      •
      Other
      •122•0•0•0•Updated Jan 31, 2018Jan 31, 2018

    • riscv-pk

      Public
      RISC-V Proxy Kernel
      C
      •
      Other
      •336•0•0•0•Updated Jan 15, 2018Jan 15, 2018

    • fpgamake

      Public
      Generates Makefiles to synthesize, place, and route verilog using Vivado
      Tcl
      •23•0•0•0•Updated Dec 14, 2017Dec 14, 2017

    • riscv-meta

      Public
      RISC-V Meta – a suite of tools that operate on RISC-V ISA (Instruction Set Architecture)
      C++
      •
      Other
      •102•8•0•0•Updated Nov 22, 2016Nov 22, 2016

    • riscv-tools

      Public
      RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
      Shell
      •446•0•0•0•Updated Jul 22, 2016Jul 22, 2016

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •365•0•0•0•Updated May 30, 2016May 30, 2016
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