Immediate support for CSR instructions？

[XuanTongYao]

When I use riscv::register::mstatus::set_mie(); to enable global interrupts, the resulting assembly code is quite puzzling.

It does not use the csrsi instruction, but instead uses the csrs instruction.
The csrs instruction uses an additional register.

This causes two problems:

1. Code bloat
2. Toggling global interrupts becomes a non-atomic operation (which contradicts the RISC-V Privileges document)

[XuanTongYao]

The same issue occurs with registers such as mie.

I'm not sure if this is the expected behavior.