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Update qtester4simd.cpp #640

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Merged
shibatch merged 1 commit into from
Feb 25, 2025
Merged

Update qtester4simd.cpp #640

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4 changes: 2 additions & 2 deletions Configure.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -98,8 +98,8 @@ endif()
# Include TLFloat as a submodule

if (SLEEF_ENABLE_TLFLOAT)
set(TLFLOAT_MINIMUM_VERSION 1.11.2)
set(TLFLOAT_GIT_TAG "356cb5ee4218fd93fbb73c76869983408b97d90a")
set(TLFLOAT_MINIMUM_VERSION 1.12.0)
set(TLFLOAT_GIT_TAG "af792e6a78e3807ec03b8eda6e17a76298acd2c9")

set(TLFLOAT_SOURCE_DIR "${PROJECT_SOURCE_DIR}/submodules/tlfloat")
set(TLFLOAT_INSTALL_DIR "${SLEEF_SUBMODULE_INSTALL_DIR}/tlfloat")
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6 changes: 3 additions & 3 deletions src/arch/helperrvv.h
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Expand Up @@ -158,14 +158,14 @@ typedef vfloat64m1x4_t tdi_t;

#define SLEEF_RVV_SP_LMUL 1
#define SLEEF_RVV_DP_LMUL 1
#define SLEEF_RVV_DP_RUNTIME_VL() __riscv_vsetvlmax_e64m1()
#define SLEEF_RVV_DP_RUNTIME_VL() ((int)__riscv_vsetvlmax_e64m1())
#if SLEEF_RVV_VLEN == 0
// The configuration didn't provide a constant vector length, meaning it'll
// have to be determined at run-time. RVV offers per-data-width operations for
// this so the result doesn't need to be adjusted and that operation is likely
// to fold into the surrounding code for free.
//
#define VECTLENSP (__riscv_vsetvlmax_e32m1())
#define VECTLENSP ((int)__riscv_vsetvlmax_e32m1())
#define VECTLENDP SLEEF_RVV_DP_RUNTIME_VL()
//@#define VECTLENSP __riscv_vsetvlmax_e32m1()
//@#define VECTLENDP __riscv_vsetvlmax_e64m1()
Expand Down Expand Up @@ -268,7 +268,7 @@ typedef vfloat64m2x4_t tdi_t;

#define SLEEF_RVV_SP_LMUL 2
#define SLEEF_RVV_DP_LMUL 2
#define SLEEF_RVV_DP_RUNTIME_VL() __riscv_vsetvlmax_e64m2()
#define SLEEF_RVV_DP_RUNTIME_VL() ((int)__riscv_vsetvlmax_e64m2())
#if SLEEF_RVV_VLEN == 0
// The configuration didn't provide a constant vector length, meaning it'll
// have to be determined at run-time. RVV offers per-data-width operations for
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4 changes: 2 additions & 2 deletions src/arch/helpersve.h
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Expand Up @@ -22,9 +22,9 @@

#if CONFIG == 1 || CONFIG == 2
// Vector length agnostic
#define VECTLENSP (svcntw())
#define VECTLENSP ((int)svcntw())
//@#define VECTLENSP (svcntw())
#define VECTLENDP (svcntd())
#define VECTLENDP ((int)svcntd())
//@#define VECTLENDP (svcntd())
#define ISANAME "AArch64 SVE"
#define ptrue svptrue_b8()
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