Add support for stm32l4r5

[gauteh]

Add support for stm32l4r5, requires: stm32-rs/stm32-rs#703

Based on #270 , also adds support for ADC1 which might be useful for r9. Not much tested yet.

[gauteh]

Test repository: https://github.com/gauteh/swan-stm32l4r5-quickstart

Flashes and runs fine with probe-run.

[gauteh]

Blinking is working, but I couldn't get the clock to work with 8Mhz: https://github.com/gauteh/swan-stm32l4r5-quickstart/blob/main/src/main.rs#L26, blinking and printing happily with the other clock though. Maybe @jspngh has an idea about whether this is supposed to work on r5 or r9?

[gauteh]

Think I understand. Default configuration the sysclk is 4MHz, so 4 / 8 becomes 0. I think this assert: https://github.com/stm32-rs/stm32l4xx-hal/blob/master/src/rcc.rs#L635 should be raised to 120Mhz. Would be interesting to see if we could make the 0 verified at compile time and not a runtime error.

[jspngh]

I can't immediately explain what's going wrong. If you have the option to step through the freeze method with gdb, it usually explains a lot of things.
For reference, here's how I configure the clocks (but with an external crystal). Being more explicit about what I wanted solved an issue in my case.

        let clocks = rcc
            .cfgr
            .hse(
                24.MHz(),
                CrystalBypass::Disable,
                ClockSecuritySystem::Disable,
            )
            .pll_source(hal::rcc::PllSource::HSE)
            .sysclk_with_pll(80.MHz(), PllConfig::new(3, 20, PllDivider::Div2))
            .pclk1(40.MHz())
            .pclk2(40.MHz())
            .freeze(&mut flash.acr, &mut pwr);

[gauteh]

Thanks, I am unfamiliar with the way of configuring the clocks. Seems like there are several roads to the same goal.

[ant32]

I'm excited for this! I got the example working on a NUCLEO-L4R5ZI that I have. I'm hoping to get USB serial working.

[DeflateAwning]

Can you explain this change? Whereas most changes in this PR only enable support, this one appears to adjust the implementation for other boards. Am especially curious about the STM32L4A6 change here.