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chipyard-chisel7.yml
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build-setup: add per-step timing table at end of run chipyard-chisel7 #32: Pull request #2312 synchronize by reed-nicolas
Action required reed-nicolas:build-setup-timing
reed-nicolas:build-setup-timing
Action required
Bump testchipip chipyard-chisel7 #31: Pull request #2331 opened by schwarz-em
5m 51s testchipip-bump-ella
testchipip-bump-ella
5m 51s
Synchronize sim success between chiptops chipyard-chisel7 #30: Pull request #2326 synchronize by schwarz-em
4m 58s multi-sim-sync
multi-sim-sync
4m 58s
fix: ensure lnuma is linked in sims chipyard-chisel7 #29: Pull request #2329 opened by jimfangx
Action required jimfangx:main
jimfangx:main
Action required
Synchronize sim success between chiptops chipyard-chisel7 #26: Pull request #2326 synchronize by schwarz-em
4m 48s multi-sim-sync
multi-sim-sync
4m 48s
rh: pinned firesim submodule commit to f2 compatible chipyard-chisel7 #25: Pull request #2327 synchronize by rickydumplings
5m 19s rickydumplings:main
rickydumplings:main
5m 19s
rh: pinned firesim submodule commit to f2 compatible chipyard-chisel7 #24: Pull request #2327 opened by rickydumplings
5m 7s rickydumplings:main
rickydumplings:main
5m 7s
Synchronize sim success between chiptops chipyard-chisel7 #23: Pull request #2326 opened by schwarz-em
6m 0s multi-sim-sync
multi-sim-sync
6m 0s
fix: pin "which" dep at 2.21 & build h0b41bf4_1 chipyard-chisel7 #22: Pull request #2325 opened by jimfangx
5m 53s jimfangx:pin-which-dep
jimfangx:pin-which-dep
5m 53s
fix single clock broadcasting binder, add option for 1 io cell per clock chipyard-chisel7 #19: Pull request #2321 opened by richardyrh
5m 0s clock-binders-iocell
clock-binders-iocell
5m 0s
Add CTC link chipyard-chisel7 #17: Pull request #2316 synchronize by schwarz-em
5m 30s ctc-bridge
ctc-bridge
5m 30s
add: supporting linux tracing and firesim tracing chipyard-chisel7 #16: Pull request #2317 opened by iansseijelly
4m 58s riscv-tacit:tacit-linux
riscv-tacit:tacit-linux
4m 58s
Add CTC link chipyard-chisel7 #15: Pull request #2316 opened by schwarz-em
5m 37s ctc-bridge
ctc-bridge
5m 37s
build-setup: add per-step timing table at end of run chipyard-chisel7 #12: Pull request #2312 opened by reed-nicolas
5m 37s reed-nicolas:build-setup-timing
reed-nicolas:build-setup-timing
5m 37s
Support sram depth/width lists, as well as explicit list of legal combos chipyard-chisel7 #10: Pull request #2303 synchronize by richardyrh
6m 14s sram-config
sram-config
6m 14s
Support sram depth/width lists, as well as explicit list of legal combos chipyard-chisel7 #9: Pull request #2303 opened by richardyrh
5m 38s sram-config
sram-config
5m 38s
Update boomv3 for rocc fix chipyard-chisel7 #8: Pull request #2250 synchronize by tianrui-wei
6m 48s boom_v3_rocc_fix
boom_v3_rocc_fix
6m 48s
fix: organize repos chipyard-chisel7 #4: Pull request #2295 opened by iansseijelly
4m 53s tacit-cleanup
tacit-cleanup
4m 53s
Experimental chisel7 support chipyard-chisel7 #3: Pull request #2293 synchronize by jerryz123
4m 48s chisel7
chisel7
4m 48s
Experimental chisel7 support chipyard-chisel7 #2: Pull request #2293 synchronize by jerryz123
5m 1s chisel7
chisel7
5m 1s
Experimental chisel7 support chipyard-chisel7 #1: Pull request #2293 synchronize by jerryz123
4m 49s chisel7
chisel7
4m 49s
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