Make plots more readable

[jordandsullivan]

Using this new mini-plot.py script, we were able to see more clearly the behavior of each individual benchmark:

Observable expectation values

Rather than our current plotting scripts, which place all benchmarks on the same Y axis for both simulation and compilation benchmarks, which is difficult to understand at times, e.g.

Compilation benchmarks

For this issue, you should

1. update our official ucc-bench plotting script to separate the different benchmarks into separate subplots, as in the mini-plot script
2. For the simulation benchmarks, add in also the uncompiled noisy expectation value so we can compare the performance of compiled vs. uncompiled circuits with noise.

[AdiBak]

Hi,
Could I please work on this issue? I'm interested in contributing to the repo and learning about quantum. Thanks!

[jordandsullivan]

Hi @AdiBak -- sure, go ahead! Feel free to reach out if you have any questions :)

[AdiBak]

Thanks!

I wanted to understand the current plotting system a bit first. Here's my understanding:

• plot_latest_benchmark.py loads results via SuiteResultsDatabase
• Compilation plots show compile_time_ms and compiled_multiq_gates for all benchmarks
• Simulation plots show relative errors (like rel_err_ideal, rel_err_noisy) for all benchmarks

And the goal is to separate each benchmark into its own subplot, with the same data/metrics (relative/absolute error), and just improve the visual organization.

Just have a few questions:

• Should the updated plots generate separate files for each metric (like, _compile-time.png, _rel-err-ideal.png) or combine them?
• Do you have any specific preferences on subplot layout?

Thanks for your time and guidance!

[jordandsullivan]

Your understanding is correct!

• I would recommend separate 3 plots for compile time, relative errors, and compiled gate ratio
• I would recommend just using a 2 x 3 grid for the layout, and you can reference the script above for more formatting issues

Thanks @AdiBak !

[AdiBak]

Hi Jordan,

Thanks for letting me know! I worked on the changes and:

• made 2x3 grid layout with individual subplots per benchmark
• added compiled gate ratio (compiled_gates / raw_gates) as third compilation metric
• generated separate files for each metric like compile-time, gate-count, gate-ratio, rel-err-ideal, rel-err-noisy

And running the latest benchmarks produced these plots:

Compilation Plots:

Simulation Plots:

Just wanted to check if these look good before submitting a PR. Thanks!

[jordandsullivan]

Thanks @AdiBak ! This is looking really good. For the compiled gates ratio, I would say we don't want to use a log plot, since the ratio generally will be between [0, 1.5]. A linear scale will be a bit clearer IMO :)

Since the ratio represents the number of gates in the original circuit / compiled gates in the final circuit, these two numbers are usually on a similar order of magnitude. Generally we want # compiled gates < # uncompiled gates, but sometimes when routing qubits on an actual quantum device, you actually end up increasing the number of compiled gates in the final circuit.

[AdiBak]

I see, thanks so much for the feedback! I updated the compiled gate ratio plot to use a linear scale instead of the log scale. The values should be clearer now as they're usually 0-1.5. I regenerated the plots as well:

Compilation:

Simulation:

[jordandsullivan]

Thanks, that looks good to me! You can go ahead and submit a PR @AdiBak !

[AdiBak]

Awesome! I just created a PR. Thanks!