mem: Add 8 channel ddr profiling

[Ergou-ren]

Change-Id: I2d3263ada2a0ee6744c4bbf387a1e6a2d9c06f69

Summary by CodeRabbit

• Chores
  • Updated DRAM simulation configuration across all workflows and utilities from 2-channel to 8-channel DDR4 setup.
  • Added new 8-channel DDR4 memory configuration file with complete timing, power, and system parameters for memory subsystem simulation.

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[coderabbitai]

📝 Walkthrough

Walkthrough

This PR updates DRAM memory configurations across multiple configuration files and scripts from a 2-channel to an 8-channel DDR4 setup. A new 8-channel DRAMSim3 configuration file is added, and all references to the 2-channel configuration are replaced with the new 8-channel configuration.

Changes

Cohort / File(s)	Summary
Workflow Configurations .github/workflows/autotest/gem5-vec.cfg, .github/workflows/autotest/gem5.cfg	Updated DRAMSim3 ini file reference from 2-channel to 8-channel configuration
Python Configuration Defaults configs/common/xiangshan.py, configs/example/se.py	Changed default DRAMSim3 ini path from 2-channel to 8-channel when no custom ini is provided
Utility Scripts util/memory_check/run-xs-with-valgrind.sh, util/pgo/basic_pgo.sh, util/runse.sh	Updated DRAM configuration references in simulation invocation commands from 2-channel to 8-channel
New DRAM Configuration ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_8ch.ini	Added complete DDR4 8-channel DRAM model configuration with timing, power, and system parameters

Suggested reviewers

• tastynoob

Poem

🐰 Eight channels wide, the memory flows,
Where DRAMSim3 now brightly glows,
From two to eight, the bandwidth grew,
With config files both old and new! 📊

Estimated code review effort

🎯 1 (Trivial) | ⏱️ ~5 minutes

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 50.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (2 passed)

Check name	Status	Explanation
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.
Title check	✅ Passed	The title accurately summarizes the main change: adding an 8-channel DDR configuration file and updating all references from 2-channel to 8-channel DRAM profiles across multiple configuration and script files.

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✨ Finishing touches

• 📝 Generate docstrings

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📜 Recent review details

Configuration used: defaults

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 024b0bf and 6973140.

📒 Files selected for processing (8)

• .github/workflows/autotest/gem5-vec.cfg
• .github/workflows/autotest/gem5.cfg
• configs/common/xiangshan.py
• configs/example/se.py
• ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_8ch.ini
• util/memory_check/run-xs-with-valgrind.sh
• util/pgo/basic_pgo.sh
• util/runse.sh

🧰 Additional context used

🧠 Learnings (1)

📚 Learning: 2025-12-16T08:28:46.184Z

Learnt from: Lingrui98
Repo: OpenXiangShan/GEM5 PR: 649
File: configs/common/xiangshan.py:0-0
Timestamp: 2025-12-16T08:28:46.184Z
Learning: In XiangShan trace mode (configs/common/xiangshan.py), there is no bootloader. Update the config by setting test_sys.workload.bootloader = '' (empty string) to indicate no bootloader, instead of providing a bootloader path. This ensures the test setup correctly reflects the absence of a bootloader for XiangShan trace mode.

Applied to files:

• configs/common/xiangshan.py

⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)

• GitHub Check: Quick Build, Unit Tests & Smoke Test

🔇 Additional comments (8)

configs/common/xiangshan.py (1)

171-174: LGTM! Default DRAMSim3 configuration updated to 8-channel.

The path update aligns with the new 8-channel configuration file added in this PR. The relative path resolution logic remains intact.

util/runse.sh (1)

24-25: LGTM! DRAMSim3 configuration path updated consistently.

The change aligns with the 8-channel configuration introduced in this PR.

.github/workflows/autotest/gem5-vec.cfg (1)

43-47: LGTM! CI workflow updated to use 8-channel DRAM configuration.

The change ensures vector tests in the autotest workflow use the new 8-channel DDR4 configuration consistently with other parts of the codebase.

configs/example/se.py (1)

162-165: LGTM! Default DRAMSim3 path updated to 8-channel configuration.

The change is consistent with the corresponding update in configs/common/xiangshan.py, ensuring both entry points default to the same 8-channel configuration when dramsim3_ini is not explicitly provided.

ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_8ch.ini (1)

1-67: Correct tCK timing value and clarify timing parameter selection.

The tCK value of 0.63 ns is incorrect for DDR4-3200; the correct value is 0.625 ns (3200 MT/s → 1600 MHz). Additionally, the timing parameters (CL=16, tRCD=18, tRP=18) deviate significantly from JEDEC DDR4-3200 baseline specifications (CL=22, tRCD=22, tRP=22). These tighter values match vendor XMP/overclocked profiles rather than standard JEDEC specifications. Clarify whether this configuration is intended to simulate an XMP profile or whether JEDEC baseline timings should be used instead.

.github/workflows/autotest/gem5.cfg (1)

188-189: LGTM - CI configuration updated to 8-channel DRAM.

The DRAMSim3 ini path in the CI workflow is correctly updated to use the 8-channel configuration, consistent with other changes in this PR.

util/memory_check/run-xs-with-valgrind.sh (1)

24-25: LGTM - Valgrind test configuration updated to 8-channel DRAM.

The DRAMSim3 ini path is correctly updated to use the 8-channel configuration, maintaining consistency with the other scripts and configurations in this PR.

util/pgo/basic_pgo.sh (1)

65-66: LGTM - Configuration updated to 8-channel DRAM.

The DRAMSim3 ini path is correctly updated to reference the 8-channel configuration file, which exists at the specified location. This aligns with the PR-wide memory configuration changes.

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[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.1691	-
This PR	2.1664	📉 -0.0027 (-0.12%)

✅ Difftest smoke test passed!

[happy-lx]

Do we still need to use 2-channel ddr in kmhv3.py?

[Ergou-ren]

Do we still need to use 2-channel ddr in kmhv3.py?

Do we still need to use 2-channel ddr in kmhv3.py?

The result of yesterday's discussion wasn't it that we should all use 8 channels temporarily?