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poemonsense
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It's becoming more clearer now. We need to find out a better way to describe different optimization passes
src/main/scala/Gateway.scala
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| val step = IO(Output(UInt(config.stepWidth.W))) | ||
| val control = Wire(new GatewaySinkControl(config)) | ||
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| val fpgaIO = Option.when(config.isFPGA)(IO(Output(new FpgaDiffIO(config)))) |
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Do you need to check whether isBatch is enabled? Otherwise, this fpgaIO is unconnected
| gateway | ||
| } | ||
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| def finishFPGA(cpu: String): FpgaDiffIO = { |
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Does the user need to call this explicitly? How does the user use this?
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Previously, users would separately generate DUT and Difftest, including variuos DifftestBundle interfaces, which we should connect manually in the wrapper module, as shown below.
https://github.com/OpenXiangShan/XiangShan/blob/7e564dbbfb630d3142a5c023ab16922e0497be9d/src/main/scala/top/Top.scala#L478-L479
This modification encapsulates DUT and Difftest, exposing only fixed-length I/O as shown below.
val difftest = DifftestModule.finishFPGA("XiangShan")
This change expose FPGA IO with finishFPGA, enabling us to wrap both DUT, Difftest, and changing DiffTestBundle Interface within the same wrapper. Only the output of Batch, with width declared at DifftestMacros.v, will be exposed to FPGA.
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This change expose FPGA IO with finishFPGA, enabling us to wrap both DUT, Difftest, and changing DiffTestBundle Interface within the same wrapper. Only the output of Batch, with width declared at DifftestMacros.v, will be exposed to FPGA.