fix(ClockGate): fix bug that ICG is invalid when disable mbist#470
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good-circle merged 1 commit intomasterfrom Feb 2, 2026
Merged
fix(ClockGate): fix bug that ICG is invalid when disable mbist#470good-circle merged 1 commit intomasterfrom
good-circle merged 1 commit intomasterfrom
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After adding DFT, if DFT is not enabled, due to the assignment `a.clock := clock`, it will directly assign the ungated clock to the SRAM that requires MCP2, causing errors. Therefore, for the `!hasMbist` case, additionally gate the clock for the SRAM. When DFT is enabled, both `wclk` and `rclk` of `mbistCgCtl` are assigned to `cg.out_clock`. Therefore, although there is the assignment `a.clock := clock`, it does not cause errors. Additionally, clock gate should always be true when enable MCP2. This commit adds the corresponding requirement check for MCP2 SRAM.
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Merge coupledL2 commits from 95e8de to 727a04c (xs/master), which is the latest on xs/master as of Mar 5, 2026. Squashed commit of the following: commit 62195c6 Author: zhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn> Date: Mon Dec 01 17:59:00 2025 +0800 timing(MainPipe): fix critical path from Dir error to GrantBuffer (OpenXiangShan#448) commit fffb491 Author: Ding Haonan <kumonda@kucro3.org> Date: Thu Dec 04 11:36:48 2025 +0800 timing(TL2CHICoupledL2): 2-stage cap P-Credit Queue (OpenXiangShan#449) commit f118bca Author: Yanqin Li <maxpicca@qq.com> Date: Tue Dec 16 21:26:05 2025 +0800 refactor: refine prefetch statistics in topdown monitor (OpenXiangShan#452) commit b40da89 Author: Ma-YX <71326427+Ma-YX@users.noreply.github.com> Date: Wed Dec 17 18:58:51 2025 +0800 fix(TXDAT): fix wrong DataCheck generation when data invalid (OpenXiangShan#455) commit e4fd161 Author: Ma-YX <71326427+Ma-YX@users.noreply.github.com> Date: Wed Dec 17 21:36:01 2025 +0800 fix(CoupledL2): fix l2MissMatch io compilation error (OpenXiangShan#456) commit 4e4a6aa Author: Kunlin You <youkunlin20@mails.ucas.ac.cn> Date: Thu Dec 18 19:13:20 2025 +0800 feat(clockGate): support disable ClockGate with parameters (OpenXiangShan#451) commit feacfb5 Author: zhaohong1988 <156632870+zhaohong1988@users.noreply.github.com> Date: Fri Dec 19 00:24:20 2025 +0800 fix(MMIOBridge): modify TIMERRange from fix value to soc parameter (OpenXiangShan#453) commit c5ad8f4 Author: Yanqin Li <maxpicca@qq.com> Date: Fri Dec 19 00:24:53 2025 +0800 ci: add submodule check and remove the dependency of utility in OpenLLC (OpenXiangShan#454) commit ea0c313 Author: Ding Haonan <kumonda@kucro3.org> Date: Fri Dec 26 09:41:32 2025 +0800 fix(MMIOBridge): remove redundant BEU range exclusion in L2 (OpenXiangShan#457) commit f292774 Author: Ding Haonan <kumonda@kucro3.org> Date: Thu Jan 08 10:15:15 2026 +0800 fix(Opcode): missing SnpPreferUniqueFwd in SnpXFwd (OpenXiangShan#460) commit 59f3025 Author: Ma-YX <71326427+Ma-YX@users.noreply.github.com> Date: Wed Jan 14 15:59:43 2026 +0800 fix(MainPipe): fix l2Error_s3 generation logic (OpenXiangShan#463) commit 3c9525f Author: Haoyuan Feng <fenghaoyuan19@mails.ucas.ac.cn> Date: Mon Feb 02 10:17:49 2026 +0800 fix(ClockGate): fix bug that ICG is invalid when disable mbist (OpenXiangShan#470) commit 0d20557 Author: yulightenyu <145419941+yulightenyu@users.noreply.github.com> Date: Tue Mar 03 14:26:16 2026 +0800 fix(AsyncBridge): restore performance considering async depth is 4 (OpenXiangShan#472) commit ef2deb5 Author: Ding Haonan <kumonda@kucro3.org> Date: Wed Mar 04 16:20:19 2026 +0800 fix(MSHR): hold LikelyShared on retried writes (OpenXiangShan#474) commit 727a04c Author: Haoyuan Feng <fenghaoyuan19@mails.ucas.ac.cn> Date: Wed Mar 04 17:01:33 2026 +0800 feat(mmioBridge): increase mmioBridgeSize to 16 for better NC perf (OpenXiangShan#475)
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After adding DFT, if DFT is not enabled, due to the assignment
a.clock := clock, it will directly assign the ungated clock to the SRAM that requires MCP2, causing errors. Therefore, for the!hasMbistcase, additionally gate the clock for the SRAM.When DFT is enabled, both
wclkandrclkofmbistCgCtlare assigned tocg.out_clock. Therefore, although there is the assignmenta.clock := clock, it does not cause errors.Additionally, clock gate should always be true when enable MCP2. This commit adds the corresponding requirement check for MCP2 SRAM.